From patchwork Thu Aug 30 19:30:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cameron Esfahani via X-Patchwork-Id: 964151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nongnu.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amazon.com header.i=@amazon.com header.b="E7ENnF5j"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 421Y1W5VZKz9s1x for ; Fri, 31 Aug 2018 05:47:43 +1000 (AEST) Received: from localhost ([::1]:50595 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSur-0002Jh-Ce for incoming@patchwork.ozlabs.org; Thu, 30 Aug 2018 15:47:41 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSt3-000139-F7 for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvSeE-0006qH-Oi for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:30:34 -0400 Received: from smtp-fw-4101.amazon.com ([72.21.198.25]:55912) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fvSeE-0006pP-HH for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:30:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535657430; x=1567193430; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=b/7VPoO0VGn0DfZi8EW/bfaP26edYDH5ok0Q73C8usc=; b=E7ENnF5jkDiKC5VClhVIxyLu6P/FGbxs1aWqzCpFNvB2Zgadb7eZ7f8K 5H+0s32mAW6GsKDBMBRfCeHuQVy4KAoyE/Zkw/hFWATuJ5PVfa6PEVNDA e1BnqwKe8MbEHXzKQKzvDTXEyf6UcSaLpCzastGEq9zfp/5LBlQJQI2H2 k=; X-IronPort-AV: E=Sophos;i="5.53,307,1531785600"; d="scan'208";a="736240523" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2a-8549039f.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-4101.iad4.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 30 Aug 2018 19:30:28 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-8549039f.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w7UJUPBn101791 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 30 Aug 2018 19:30:26 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7UJUP18020250; Thu, 30 Aug 2018 15:30:25 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7UJUPcY020249; Thu, 30 Aug 2018 15:30:25 -0400 To: qemu-devel@nongnu.org Date: Thu, 30 Aug 2018 15:30:18 -0400 Message-Id: <20180830193019.20104-9-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830193019.20104-1-jancraig@amazon.com> References: <20180830193019.20104-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 72.21.198.25 Subject: [Qemu-devel] [PATCH v4 8/9] target/mips: Add MXU instructions Q8MUL and Q8MULSU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Craig Janeczek via Qemu-devel From: Cameron Esfahani via Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Adds support for emulating the Q8MUL and Q8MULSU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 - Add check for MXUEN target/mips/translate.c | 95 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index ea6484e2db..31c7342261 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4131,6 +4131,97 @@ static void gen_mxu_d16mac(DisasContext *ctx, uint32_t opc) tcg_temp_free(t3); } +/* Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply */ +/* Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply */ +static void gen_mxu_q8mul(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1, t2, t3, t4, t5, t6, t7; + TCGLabel *l0; + uint32_t xra, xrb, xrc, xrd, sel; + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + t4 = tcg_temp_new(); + t5 = tcg_temp_new(); + t6 = tcg_temp_new(); + t7 = tcg_temp_new(); + + l0 = gen_new_label(); + + xra = extract32(ctx->opcode, 6, 4); + xrb = extract32(ctx->opcode, 10, 4); + xrc = extract32(ctx->opcode, 14, 4); + xrd = extract32(ctx->opcode, 18, 4); + sel = extract32(ctx->opcode, 22, 4); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_mxu_gpr(t3, xrb); + gen_load_mxu_gpr(t7, xrc); + + if (sel == 0x2) { + /* Q8MULSU */ + tcg_gen_ext8s_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t3, t3); + } else { + /* Q8MUL */ + tcg_gen_ext8u_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t3, t3); + } + + tcg_gen_ext8u_tl(t4, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t5, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t6, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t7, t7); + + tcg_gen_mul_tl(t0, t0, t4); + tcg_gen_mul_tl(t1, t1, t5); + tcg_gen_mul_tl(t2, t2, t6); + tcg_gen_mul_tl(t3, t3, t7); + + tcg_gen_andi_tl(t0, t0, 0xFFFF); + tcg_gen_andi_tl(t1, t1, 0xFFFF); + tcg_gen_andi_tl(t2, t2, 0xFFFF); + tcg_gen_andi_tl(t3, t3, 0xFFFF); + + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_shli_tl(t3, t3, 16); + + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_tl(t1, t2, t3); + + gen_store_mxu_gpr(t0, xrd); + gen_store_mxu_gpr(t1, xra); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + tcg_temp_free(t4); + tcg_temp_free(t5); + tcg_temp_free(t6); + tcg_temp_free(t7); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18215,6 +18306,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *env, DisasContext *ctx) gen_mxu_d16mac(ctx, op1); break; + case OPC_MXU_Q8MUL: + gen_mxu_q8mul(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI);