[v3,4/8] target/mips: Add MXU instruction S8LDD

Adds support for emulating the S8LDD MXU instruction.

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
---
 v1
    - initial patch
 v2
    - changed bitfield usage to extract32
    - used deposit_tl instructions instead of shift and bitmask
 v3
    - Split gen_mxu function into command specific gen_mxu_<ins> functions

 target/mips/translate.c | 69 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

> From: Craig Janeczek <jancraig@amazon.com>
> Sent: Tuesday, August 28, 2018 3:00 PM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic; aurelien@aurel32.net; Craig Janeczek
> Subject: [PATCH v3 4/8] target/mips: Add MXU instruction S8LDD
> 
> Adds support for emulating the S8LDD MXU instruction.
> 
> Signed-off-by: Craig Janeczek <jancraig@amazon.com>
> ---
>  v1
>     - initial patch
>  v2
>     - changed bitfield usage to extract32
>     - used deposit_tl instructions instead of shift and bitmask
>  v3
>     - Split gen_mxu function into command specific gen_mxu_<ins> functions
> 
>  target/mips/translate.c | 69 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index f6991aa8ef..024e48baf6 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -3851,6 +3851,71 @@ static void gen_mxu_s32m2i(DisasContext *ctx, uint32_t opc)
>      tcg_temp_free(t0);
>  }
> 
> +/* S8LDD XRa, rb, S8, OPTN3 - Load a byte from memory to XRF */
> +static void gen_mxu_s8ldd(DisasContext *ctx, uint32_t opc)
> +{
> +    TCGv t0, t1;
> +    uint32_t xra, s8, optn3, rb;
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +
> +    xra = extract32(ctx->opcode, 6, 4);
> +    s8 = extract32(ctx->opcode, 10, 8);
> +    optn3 = extract32(ctx->opcode, 18, 3);
> +    rb = extract32(ctx->opcode, 21, 5);
> +
> +    gen_load_gpr(t0, rb);
> +    tcg_gen_addi_tl(t0, t0, (int8_t)s8);
> +    switch (optn3) {
> +    case 0: /*XRa[7:0] = tmp8 */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
> +        gen_load_mxu_gpr(t0, xra);
> +        tcg_gen_deposit_tl(t0, t0, t1, 0, 8);
> +        break;
> +    case 1: /* XRa[15:8] = tmp8 */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
> +        gen_load_mxu_gpr(t0, xra);
> +        tcg_gen_deposit_tl(t0, t0, t1, 8, 8);
> +        break;
> +    case 2: /* XRa[23:16] = tmp8 */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
> +        gen_load_mxu_gpr(t0, xra);
> +        tcg_gen_deposit_tl(t0, t0, t1, 16, 8);
> +        break;
> +    case 3: /* XRa[31:24] = tmp8 */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
> +        gen_load_mxu_gpr(t0, xra);
> +        tcg_gen_deposit_tl(t0, t0, t1, 24, 8);
> +        break;
> +    case 4: /* XRa = {8'b0, tmp8, 8'b0, tmp8} */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
> +        tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
> +        break;
> +    case 5: /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
> +        tcg_gen_shli_tl(t1, t1, 8);
> +        tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
> +        break;
> +    case 6: /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);
> +        tcg_gen_mov_tl(t0, t1);
> +        tcg_gen_andi_tl(t0, t0, 0xFF00FFFF);
> +        tcg_gen_shli_tl(t1, t1, 16);
> +        tcg_gen_or_tl(t0, t0, t1);
> +        break;
> +    case 7: /* XRa = {tmp8, tmp8, tmp8, tmp8} */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
> +        tcg_gen_deposit_tl(t1, t1, t1, 8, 8);
> +        tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
> +        break;
> +    }

Similar to the situation in patch 6, the following is missing:

/* MXU operand getting patterns OPTN3 */
#define MXU_OPTN3_PTN0  0
#define MXU_OPTN3_PTN1  1
#define MXU_OPTN3_PTN2  2
#define MXU_OPTN3_PTN3  3
#define MXU_OPTN3_PTN4  4
#define MXU_OPTN3_PTN5  5
#define MXU_OPTN3_PTN6  6
#define MXU_OPTN3_PTN7  7

> +    gen_store_mxu_gpr(t0, xra);
> +
> +    tcg_temp_free(t0);
> +    tcg_temp_free(t1);
> +}
> +
>  /* Godson integer instructions */
>  static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
>                                   int rd, int rs, int rt)
> @@ -17956,6 +18021,10 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
>          gen_mxu_s32m2i(ctx, op1);
>          break;
> 
> +    case OPC_MXU_S8LDD:
> +        gen_mxu_s8ldd(ctx, op1);
> +        break;
> +
>      case OPC_CLO:
>      case OPC_CLZ:
>          check_insn(ctx, ISA_MIPS32);
> --
> 2.18.0
> 

Thanks,
Aleksandar

On 08/28/2018 06:00 AM, Craig Janeczek via Qemu-devel wrote:
> +    case 6: /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */
> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);
> +        tcg_gen_mov_tl(t0, t1);
> +        tcg_gen_andi_tl(t0, t0, 0xFF00FFFF);
> +        tcg_gen_shli_tl(t1, t1, 16);
> +        tcg_gen_or_tl(t0, t0, t1);
> +        break;

 tcg_gen_deposit_tl(t0, t1, t1, 16, 16);


r~