From patchwork Mon Aug 27 14:38:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cameron Esfahani via X-Patchwork-Id: 962544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nongnu.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amazon.com header.i=@amazon.com header.b="qddAvzl9"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41zZP75rbBz9s3x for ; Tue, 28 Aug 2018 00:42:51 +1000 (AEST) Received: from localhost ([::1]:53558 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuIjB-0006Li-FK for incoming@patchwork.ozlabs.org; Mon, 27 Aug 2018 10:42:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46199) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuIiN-0006CA-0v for qemu-devel@nongnu.org; Mon, 27 Aug 2018 10:42:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fuIiI-00026e-Tl for qemu-devel@nongnu.org; Mon, 27 Aug 2018 10:41:58 -0400 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:30130) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fuIiI-000260-H2 for qemu-devel@nongnu.org; Mon, 27 Aug 2018 10:41:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535380914; x=1566916914; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=y6ev9x/wZ7hu4RvN064OGvMHSS1peu1u/tFErNhIOic=; b=qddAvzl9kRO0bNKnOSDzQ0JXKt07zn2fOdgPJbnv2OX6nrUyUNI5pHzk U9c/6bHLyccAJscF+kkI6YYVjCJYzVBUctVPCCvZpvX5DFBR/rnKCgRKU dkiOxnCk+U1Co4dR+jABmV5O8Ju74qyjFoxPZ19z8EOcDCovgNUI0vb8H o=; X-IronPort-AV: E=Sophos;i="5.53,295,1531785600"; d="scan'208";a="750831319" Received: from sea3-co-svc-lb6-vlan2.sea.amazon.com (HELO email-inbound-relay-1a-7d76a15f.us-east-1.amazon.com) ([10.47.22.34]) by smtp-border-fw-out-33001.sea14.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 27 Aug 2018 14:39:33 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (iad7-ws-svc-lb50-vlan2.amazon.com [10.0.93.210]) by email-inbound-relay-1a-7d76a15f.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id w7REcK61076283 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 27 Aug 2018 14:38:21 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7REcKI7025134; Mon, 27 Aug 2018 10:38:20 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7REcKJd025133; Mon, 27 Aug 2018 10:38:20 -0400 To: qemu-devel@nongnu.org Date: Mon, 27 Aug 2018 10:38:01 -0400 Message-Id: <20180827143806.25048-2-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180827143806.25048-1-jancraig@amazon.com> References: <20180827143806.25048-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v2 1/6] target/mips: Add MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Craig Janeczek via Qemu-devel From: Cameron Esfahani via Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This commit makes the MXU registers and the utility functions for reading/writing to them. This is required for full MXU instruction support. Adds support for emulating the S32I2M and S32M2I MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - Fix checkpatch.pl errors - remove mips64 ifdef - changed bitfield usage to extract32 - squashed register addition patch into this one target/mips/cpu.h | 1 + target/mips/translate.c | 71 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202cf64..4b2948a2c8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -170,6 +170,7 @@ struct TCState { MSACSR_FS_MASK) float_status msa_fp_status; + target_ulong mxu_gpr[16]; }; typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index bdd880bb77..ef819d67e0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -364,6 +364,9 @@ enum { OPC_CLO = 0x21 | OPC_SPECIAL2, OPC_DCLZ = 0x24 | OPC_SPECIAL2, OPC_DCLO = 0x25 | OPC_SPECIAL2, + /* MXU */ + OPC_MXU_S32I2M = 0x2F | OPC_SPECIAL2, + OPC_MXU_S32M2I = 0x2E | OPC_SPECIAL2, /* Special */ OPC_SDBBP = 0x3F | OPC_SPECIAL2, }; @@ -1398,6 +1401,9 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; +/* MXU registers */ +static TCGv mxu_gpr[16]; + #include "exec/gen-icount.h" #define gen_helper_0e0i(name, arg) do { \ @@ -1517,6 +1523,13 @@ static const char * const msaregnames[] = { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; +static const char * const mxuregnames[] = { + "XR1", "XR2", "XR3", "XR4", "XR5", + "XR6", "XR7", "XR8", "XR9", "XR10", + "XR11", "XR12", "XR13", "XR14", "XR15", + "XR16", +}; + #define LOG_DISAS(...) \ do { \ if (MIPS_DEBUG_DISAS) { \ @@ -1550,6 +1563,23 @@ static inline void gen_store_gpr (TCGv t, int reg) tcg_gen_mov_tl(cpu_gpr[reg], t); } +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, int reg) +{ + if (reg == 0) { + tcg_gen_movi_tl(t, 0); + } else { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, int reg) +{ + if (reg != 0) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr (int from, int to) { @@ -3738,6 +3768,35 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, } } +/* MXU Instructions */ +static void gen_mxu(DisasContext *ctx, uint32_t opc) +{ + TCGv t0; + uint32_t xra, rb; + + t0 = tcg_temp_new(); + + switch (opc) { + case OPC_MXU_S32I2M: + xra = extract32(ctx->opcode, 6, 5); + rb = extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, rb); + gen_store_mxu_gpr(t0, xra); + break; + + case OPC_MXU_S32M2I: + xra = extract32(ctx->opcode, 6, 5); + rb = extract32(ctx->opcode, 16, 5); + + gen_load_mxu_gpr(t0, xra); + gen_store_gpr(t0, rb); + break; + } + + tcg_temp_free(t0); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -17818,6 +17877,12 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) check_insn(ctx, INSN_LOONGSON2F); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + + case OPC_MXU_S32I2M: + case OPC_MXU_S32M2I: + gen_mxu(ctx, op1); + break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32); @@ -20742,6 +20807,12 @@ void mips_tcg_init(void) fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); + + for (i = 0; i < 16; i++) + mxu_gpr[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, + active_tc.mxu_gpr[i]), + mxuregnames[i]); } #include "translate_init.inc.c"