| Message ID | 20180809034033.10579-9-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: sve linux-user patches | expand |
On Thu, Aug 9, 2018 at 5:40 AM, Richard Henderson <richard.henderson@linaro.org> wrote: > The scaling should be solely on the memory operation size; the number > of registers being loaded does not come in to the initial computation. > > Cc: qemu-stable@nongnu.org (3.0.1) > Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Laurent > --- > target/arm/translate-sve.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c > index f635822a61..d27bc8c946 100644 > --- a/target/arm/translate-sve.c > +++ b/target/arm/translate-sve.c > @@ -4665,8 +4665,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn) > } > if (sve_access_check(s)) { > TCGv_i64 addr = new_tmp_a64(s); > - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), > - (a->nreg + 1) << dtype_msz(a->dtype)); > + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); > tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); > do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); > } > @@ -4899,7 +4898,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn) > } > if (sve_access_check(s)) { > TCGv_i64 addr = new_tmp_a64(s); > - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz); > + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); > tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); > do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); > } > -- > 2.17.1 >
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f635822a61..d27bc8c946 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4665,8 +4665,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn) } if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), - (a->nreg + 1) << dtype_msz(a->dtype)); + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); } @@ -4899,7 +4898,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn) } if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz); + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); }
The scaling should be solely on the memory operation size; the number of registers being loaded does not come in to the initial computation. Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-sve.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)