| Message ID | 20180809034033.10579-10-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: sve linux-user patches | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > With PC, there are 33 registers. Three per line lines up nicely > without overflowing 80 columns. > > Cc: qemu-stable@nongnu.org (3.0.1) > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/translate-a64.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 45a6c2a3aa..358f169c75 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -137,14 +137,13 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > int el = arm_current_el(env); > const char *ns_status; > > - cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", > - env->pc, env->xregs[31]); > - for (i = 0; i < 31; i++) { > - cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); > - if ((i % 4) == 3) { > - cpu_fprintf(f, "\n"); > + cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); > + for (i = 0; i < 32; i++) { > + if (i == 31) { > + cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); > } else { > - cpu_fprintf(f, " "); > + cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], > + (i + 2) % 3 ? " " : "\n"); > } > } -- Alex Bennée
Richard Henderson <richard.henderson@linaro.org> writes: > With PC, there are 33 registers. Three per line lines up nicely > without overflowing 80 columns. > > Cc: qemu-stable@nongnu.org (3.0.1) > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/translate-a64.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 45a6c2a3aa..358f169c75 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -137,14 +137,13 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > int el = arm_current_el(env); > const char *ns_status; > > - cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", > - env->pc, env->xregs[31]); > - for (i = 0; i < 31; i++) { > - cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); > - if ((i % 4) == 3) { > - cpu_fprintf(f, "\n"); > + cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); > + for (i = 0; i < 32; i++) { > + if (i == 31) { > + cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); > } else { > - cpu_fprintf(f, " "); > + cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], > + (i + 2) % 3 ? " " : "\n"); > } > } -- Alex Bennée
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 45a6c2a3aa..358f169c75 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -137,14 +137,13 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int el = arm_current_el(env); const char *ns_status; - cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", - env->pc, env->xregs[31]); - for (i = 0; i < 31; i++) { - cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); - if ((i % 4) == 3) { - cpu_fprintf(f, "\n"); + cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); + for (i = 0; i < 32; i++) { + if (i == 31) { + cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); } else { - cpu_fprintf(f, " "); + cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], + (i + 2) % 3 ? " " : "\n"); } }
With PC, there are 33 registers. Three per line lines up nicely without overflowing 80 columns. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-a64.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-)