From patchwork Wed Jun 20 12:05:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 932131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mips.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 419kJr547Nz9s4w for ; Wed, 20 Jun 2018 22:14:04 +1000 (AEST) Received: from localhost ([::1]:49026 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbzt-0007qF-R6 for incoming@patchwork.ozlabs.org; Wed, 20 Jun 2018 08:14:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbuM-0003Ec-L6 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbuI-0003xL-Lg for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:18 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:35087) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbuI-0003sq-FF for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:14 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx2.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:08:04 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:08:01 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:50 +0100 Message-ID: <20180620120620.12806-6-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496484-298553-23331-42495-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 05/35] target/mips: Add nanoMIPS 16bit ld/st instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add nanoMIPS 16bit load and store instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 633d0b4..f5b7e14 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16207,6 +16207,14 @@ static int mmreg_nanomips(int r) return map[r & 0x7]; } +/* Used for 16-bit store instructions. */ +static int mmreg2_nanomips(int r) +{ + static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + static int mmreg4_nanomips(int r) { static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7, @@ -16292,6 +16300,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P16C: + switch (ctx->opcode & 1) { + case NM_POOL16C_0: + break; + case NM_LWXS16: + gen_ldxs(ctx, rt, rs, rd); + break; + } break; case NM_P16_A1: switch ((ctx->opcode >> 6) & 1) { @@ -16375,24 +16390,119 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P16_LB: + { + uint32_t u = extract32(ctx->opcode, 0, 2); + switch (((ctx->opcode) >> 2) & 0x03) { + case NM_LB16: + gen_ld(ctx, OPC_LB, rt, rs, u); + break; + case NM_SB16: + { + int rt = mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + gen_st(ctx, OPC_SB, rt, rs, u); + } + break; + case NM_LBU16: + gen_ld(ctx, OPC_LBU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P16_LH: + { + uint32_t u = extract32(ctx->opcode, 1, 2) << 1; + switch ((((ctx->opcode >> 3) & 1) << 1) | (ctx->opcode & 1)) { + case NM_LH16: + gen_ld(ctx, OPC_LH, rt, rs, u); + break; + case NM_SH16: + { + int rt = mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + gen_st(ctx, OPC_SH, rt, rs, u); + } + break; + case NM_LHU16: + gen_ld(ctx, OPC_LHU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_LW16: + { + int u = extract32(ctx->opcode, 0, 4) << 2; + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_LWSP16: + { + int rt = uMIPS_RD5(ctx->opcode); + int u = extract32(ctx->opcode, 0, 5) << 2; + + gen_ld(ctx, OPC_LW, rt, 29, u); + } break; case NM_LW4X4: + { + int rt = (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs = (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u = (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt = mmreg4_nanomips(rt); + rs = mmreg4_nanomips(rs); + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_SW4X4: + { + int rt = (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs = (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u = (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt = mmreg4z_nanomips(rt); + rs = mmreg4_nanomips(rs); + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_LWGP16: + { + int u = extract32(ctx->opcode, 0, 7) << 2; + gen_ld(ctx, OPC_LW, rt, 28, u); + } break; case NM_SWSP16: + { + int rt = uMIPS_RD5(ctx->opcode); + int u = extract32(ctx->opcode, 0, 5) << 2; + + gen_st(ctx, OPC_SW, rt, 29, u); + } break; case NM_SW16: + { + int rt = mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + int rs = mmreg_nanomips(uMIPS_RS(ctx->opcode)); + int u = extract32(ctx->opcode, 0, 4) << 2; + + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_SWGP16: + { + int rt = mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + int u = extract32(ctx->opcode, 0, 7) << 2; + + gen_st(ctx, OPC_SW, rt, 28, u); + } break; case NM_BC16: gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,