From patchwork Tue May 8 17:31:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 910380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="prBIRg1S"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40gRnC59nwz9rxs for ; Wed, 9 May 2018 03:49:02 +1000 (AEST) Received: from localhost ([::1]:52649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6jS-0000wY-RR for incoming@patchwork.ozlabs.org; Tue, 08 May 2018 13:48:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44212) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6Tc-00008h-8s for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG6Ta-0005Xs-Je for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:36 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:36827) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fG6Ta-0005Xc-C1 for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:34 -0400 Received: by mail-lf0-x242.google.com with SMTP id t129-v6so7740827lff.3 for ; Tue, 08 May 2018 10:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LuNcbqSjKxB1BfScpas0UwL9xk+DXRuan/kipFw620k=; b=prBIRg1SZQoWxU8ObLBBKu0eYDxb+0JhJRhPKE5dIHFq+jrfslFck6maDz4BkCPn3x Y7lA3Hkhonc7BWx3/vlhh2I/Vkc1JM8OC9UjyiOxTorWZJ05F3f5bdIdrC5KM+BiPpvt hMrb0N5GfLBHLD3mKPp31DYda2JAEeFDeww965s+yZdrOLqKBSWY4CkzteCk+8NI+Bir cnAqt6vWpV7AhZ0/l5UMjEq2Pkogz7CoSPMURLFFMFcNL1dvSD+DtlrSEg+syl39C1vV Due2ZLv7bfykRHxTXtbjCIvNf2ufb8TKqxPR8H+/iStVz3l/ichgPO80+rNlee0R9wf0 2PJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LuNcbqSjKxB1BfScpas0UwL9xk+DXRuan/kipFw620k=; b=FMZcm3/RGmmlCBBi0FqqF7AOjpCt4RlrBDjWa/tSinmMt3sD//AtpyTolpWKWqsn+f YBfgMuO6jVaTUoqTNj2uddLkMwid1im55XRxXEUR84BAs41alyB8KEMHN+e2YaUgGMb/ ypuVctqONgj8fNg0lXj8w5+cFIcMn05d82ja38oOb4LZwSgd9ucHpjSJKNUMSYvDtsP0 bWnLfZYIyqOQj4JZSqyzQyIepA2S/uvsJ3oRrsEVNYdYcCqplSgNqdLBZ3X/QtiLHtTl P3aiP+Wrdopm6QcHSknEIBiW/fM1/3QnIj2lD9zSsF3npGLZ+Oej1xB2oled4jIV22rm 4/hA== X-Gm-Message-State: ALKqPwfHYt8DmuJwxrC31jPKXmf5QoxlHZB43J8t+JwZc6c7m8xf/H8W cU2kSzIhXqBj2a5ui5r7m++gJQ== X-Google-Smtp-Source: AB8JxZqQ3m3NFctYagpFT+4CnYMyt6wXGdzMno0H3A0km37RvVAJLHCm2KsynuQykFANoAISnz2OYg== X-Received: by 2002:a19:e4d6:: with SMTP id x83-v6mr1873633lfi.10.1525800752875; Tue, 08 May 2018 10:32:32 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id o82-v6sm4837585lja.67.2018.05.08.10.32.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 10:32:31 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 19:31:41 +0200 Message-Id: <20180508173152.29327-26-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180508173152.29327-1-edgar.iglesias@gmail.com> References: <20180508173152.29327-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v2 25/36] target-microblaze: mmu: Remove unused register state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add explicit handling for MMU_R_TLBX and log accesses to invalid MMU registers. We can now remove the state for all regs but PID, ZPR and TLBX (0 - 2). Signed-off-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/microblaze/mmu.c | 7 +++++-- target/microblaze/mmu.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index f4a4c339c9..231803ceea 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -211,11 +211,14 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) } r = env->mmu.regs[rn]; break; + case MMU_R_TLBX: + r = env->mmu.regs[rn]; + break; case MMU_R_TLBSX: qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); break; default: - r = env->mmu.regs[rn]; + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); break; } D(qemu_log("%s rn=%d=%x\n", __func__, rn, r)); @@ -298,7 +301,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) break; } default: - env->mmu.regs[rn] = v; + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); break; } } diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 113539c6e9..624becfded 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -67,7 +67,7 @@ struct microblaze_mmu /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ uint8_t tids[TLB_ENTRIES]; /* Control flops. */ - uint32_t regs[8]; + uint32_t regs[3]; int c_mmu; int c_mmu_tlb_access;