From patchwork Tue May 8 15:14:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 910281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="C+/sOXwV"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40gNZk5nZdz9s0W for ; Wed, 9 May 2018 01:24:46 +1000 (AEST) Received: from localhost ([::1]:51861 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG4Ts-0005ge-Ay for incoming@patchwork.ozlabs.org; Tue, 08 May 2018 11:24:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG4KM-0006hY-U9 for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG4KK-0008Fs-9T for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:54 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:35145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fG4KK-0008Ex-4m for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:52 -0400 Received: by mail-pl0-x241.google.com with SMTP id i5-v6so2416543plt.2 for ; Tue, 08 May 2018 08:14:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8rcPASnE+C7rW9/bI3AEK2ZVz+3GRCpBYozOZLaQ8f8=; b=C+/sOXwV2h4jn9oE5bnTe/cCvgX58TgMsBIEL9aKnhhG6Lc0QjddF83W/oxnsnLvap SkKtaINBwAA3akK5I35xYoWfqq7+UFZ0TSkcCRdx+gH5OlDj4LEHRicQUlaOBiqbEO2L gZAlPS/JAW5pg8Fr0JZRPY9VRzr0icu/gkdOo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8rcPASnE+C7rW9/bI3AEK2ZVz+3GRCpBYozOZLaQ8f8=; b=Ud6HruYv7Tx+q30xEb/Pzs8EiuYklV3pf3bEWteeMBjl84PsLe4V/EeRpyKYqKAGJr L6UTvSLeRgbyyr0fvX8MQ82tyoWKAVfzIatrffN5GCGZ7YteRFJ1bgPmdymjudsssQif NTYqTEVe2IS2N9KPc2hEtjd0Y9UCFSegnbATl8cIk2nRFx97u6kj2AWMnD2cOEgxavMA tjnFMu5Hv3XAdHLtsnSd48rR8V7cRV65AgSa7N3giTH+Q2iTSKUT7TmZ7qTtUCVnItF0 AgN1GAsuwRhxAG4Tt7ThLagbnKYL9KIurKopP5Nc99UvXU5hWIidEqQdBdi6kBOq574S yqnA== X-Gm-Message-State: ALQs6tAfyhotg5PRxnvHy1yS+RtsWcQYC6ktBtyjoPMj5whSWqor5eMv DwGhkTu31KXcxxtS+P4fkpjKxjiFe0s= X-Google-Smtp-Source: AB8JxZo8BRmeaGpcoxz2HoKj317PBr9tN+QaXT5KBdl+dxDDxU3cUJ14rH6pegeqUJlMICwWIdX4UA== X-Received: by 2002:a17:902:b485:: with SMTP id y5-v6mr10138235plr.381.1525792490916; Tue, 08 May 2018 08:14:50 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id n10sm55598896pfj.68.2018.05.08.08.14.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 08:14:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 08:14:35 -0700 Message-Id: <20180508151437.4232-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508151437.4232-1-richard.henderson@linaro.org> References: <20180508151437.4232-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 08/10] target/arm: Fill in disas_ldst_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This implements all of the v8.1-Atomics instructions except for compare-and-swap, which is decoded elsewhere. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6acad791e6..c13858a690 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -84,6 +84,7 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); +typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp); /* Note that the gvec expanders operate on offsets + sizes. */ typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); @@ -2772,6 +2773,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, int rn = extract32(insn, 5, 5); int o3_opc = extract32(insn, 12, 4); int feature = ARM_FEATURE_V8_ATOMICS; + TCGv_i64 tcg_rn, tcg_rs; + AtomicThreeOpFn *fn; if (is_vector) { unallocated_encoding(s); @@ -2779,14 +2782,32 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, } switch (o3_opc) { case 000: /* LDADD */ + fn = tcg_gen_atomic_fetch_add_i64; + break; case 001: /* LDCLR */ + fn = tcg_gen_atomic_fetch_and_i64; + break; case 002: /* LDEOR */ + fn = tcg_gen_atomic_fetch_xor_i64; + break; case 003: /* LDSET */ + fn = tcg_gen_atomic_fetch_or_i64; + break; case 004: /* LDSMAX */ + fn = tcg_gen_atomic_fetch_smax_i64; + break; case 005: /* LDSMIN */ + fn = tcg_gen_atomic_fetch_smin_i64; + break; case 006: /* LDUMAX */ + fn = tcg_gen_atomic_fetch_umax_i64; + break; case 007: /* LDUMIN */ + fn = tcg_gen_atomic_fetch_umin_i64; + break; case 010: /* SWP */ + fn = tcg_gen_atomic_xchg_i64; + break; default: unallocated_encoding(s); return; @@ -2796,8 +2817,21 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, return; } - (void)rs; - (void)rn; + if (rn == 31) { + gen_check_sp_alignment(s); + } + tcg_rn = cpu_reg_sp(s, rn); + tcg_rs = read_cpu_reg(s, rs, true); + + if (o3_opc == 1) { /* LDCLR */ + tcg_gen_not_i64(tcg_rs, tcg_rs); + } + + /* The tcg atomic primitives are all full barriers. Therefore we + * can ignore the Acquire and Release bits of this instruction. + */ + fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s), + s->be_data | size | MO_ALIGN); } /* Load/store register (all forms) */