From patchwork Tue May 8 15:14:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 910277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="EoDaCnXQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40gNWs6gVkz9s27 for ; Wed, 9 May 2018 01:22:17 +1000 (AEST) Received: from localhost ([::1]:51846 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG4RT-0003PL-D7 for incoming@patchwork.ozlabs.org; Tue, 08 May 2018 11:22:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG4KC-0006Xf-VO for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG4KB-000870-L1 for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:44 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:32940) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fG4KB-00086K-Ct for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:43 -0400 Received: by mail-pf0-x243.google.com with SMTP id f20so15325000pfn.0 for ; Tue, 08 May 2018 08:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPbKyRbGHUC+ZTBbJLdOh2b1BPPW3PUldr8irMjIU1o=; b=EoDaCnXQMnPI1/jT/3Ak2hHHdPktlHZ4/W2fshpXlZ/gJi4WJNYhJgEwEiytKhi2q5 GGPGGbYGpmwDhMWAeAd1g+qGhcs1AUpDfCa6Jj4Pg9Mzit7OMGQ1i1/1pA7PIcFPiNRY 8BKNUdunjOy0756vuLwDR7nq4oDublViqKx74= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPbKyRbGHUC+ZTBbJLdOh2b1BPPW3PUldr8irMjIU1o=; b=S9gzlhq90iySHt4zdalQjTGXzZ08NzUPJ8wvq2ATp5pLp6SJcnx6Awnqz8AHPUclag 1rU3NCksl6XIN5oe1YDEIsOUawO+oC5mfpomZeUV1stoeLsgWNS74AJYomXoVd6f9PuT 9k7gJq4EjolZdKOGtbqgEQH5QNY8DREoig6pWSWTb6ESbKODaeSLcNTSc74LWr3vxl8s kiRiFQEzCe60RVXoSpkq09J9acr/IqT+6w+VYScexqEEtUSoQ/tbDxhvetzqIfb1U/UJ +vbzMRTItYMA4v0m2PELKgOFR97PEsn9mnl1q2CdQK2DSK2Sj3U4+zNzDPwfWa1bO8Kf xVrA== X-Gm-Message-State: ALQs6tDVbPdyYPtgv4dDVxGhyBHF16kh3AO0U/sSQq3NPlNaPvSR5ASK PVn3PM3bnYWkgE2M6sUIEiuGqFSmC4M= X-Google-Smtp-Source: AB8JxZodUUhy4fM8ExmEOV6347+Dfn+WpWoZR8iccHIbFWesc6y2bZJ3e/cJp5Qa+c5/nl8UXXdqog== X-Received: by 10.98.229.13 with SMTP id n13mr40432641pff.125.1525792482064; Tue, 08 May 2018 08:14:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id n10sm55598896pfj.68.2018.05.08.08.14.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 08:14:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 08:14:29 -0700 Message-Id: <20180508151437.4232-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508151437.4232-1-richard.henderson@linaro.org> References: <20180508151437.4232-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 02/10] target/arm: Use new min/max expanders X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The generic expanders replace nearly identical code in the translator. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 46 ++++++++++++-------------------------- 1 file changed, 14 insertions(+), 32 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bff4e13bf6..d916fea3a3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6021,15 +6021,18 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); break; case 0x0a: /* SMAXV / UMAXV */ - tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, - tcg_res, - tcg_res, tcg_elt, tcg_res, tcg_elt); + if (is_u) { + tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); + } else { + tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); + } break; case 0x1a: /* SMINV / UMINV */ - tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE, - tcg_res, - tcg_res, tcg_elt, tcg_res, tcg_elt); - break; + if (is_u) { + tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); + } else { + tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); + } break; default: g_assert_not_reached(); @@ -9931,27 +9934,6 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) } } -/* Helper functions for 32 bit comparisons */ -static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2); -} - -static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2); -} - -static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2); -} - -static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2); -} - /* Pairwise op subgroup of C3.6.16. * * This is called directly or via the handle_3same_float for float pairwise @@ -10051,7 +10033,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, static NeonGenTwoOpFn * const fns[3][2] = { { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, - { gen_max_s32, gen_max_u32 }, + { tcg_gen_smax_i32, tcg_gen_umax_i32 }, }; genfn = fns[size][u]; break; @@ -10061,7 +10043,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, static NeonGenTwoOpFn * const fns[3][2] = { { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, - { gen_min_s32, gen_min_u32 }, + { tcg_gen_smin_i32, tcg_gen_umin_i32 }, }; genfn = fns[size][u]; break; @@ -10516,7 +10498,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) static NeonGenTwoOpFn * const fns[3][2] = { { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, - { gen_max_s32, gen_max_u32 }, + { tcg_gen_smax_i32, tcg_gen_umax_i32 }, }; genfn = fns[size][u]; break; @@ -10527,7 +10509,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) static NeonGenTwoOpFn * const fns[3][2] = { { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, - { gen_min_s32, gen_min_u32 }, + { tcg_gen_smin_i32, tcg_gen_umin_i32 }, }; genfn = fns[size][u]; break;