mbox

[PULL,00/42] target-arm queue

Message ID 20180301112403.12487-1-peter.maydell@linaro.org
State New
Headers show

Pull-request

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301

Message

Peter Maydell March 1, 2018, 11:23 a.m. UTC 
Arm queue -- I have more stuff pending but I prefer to push
this first lot out and keep the pull below 50 patches.
Most of this is Alex's FP16 support work.

-- PMM


The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:

  Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)

are available in the Git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301

for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:

  MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)

----------------------------------------------------------------
target-arm queue:
 * update MAINTAINERS for Alistair's new email address
 * add Arm v8.2 FP16 arithmetic extension for linux-user
 * implement display connector emulation for vexpress board
 * xilinx_spips: Enable only two slaves when reading/writing with stripe
 * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
 * hw: register: Run post_write hook on reset

----------------------------------------------------------------
Alex Bennée (31):
      include/exec/helper-head.h: support f16 in helper calls
      target/arm/cpu64: introduce ARM_V8_FP16 feature bit
      target/arm/cpu.h: update comment for half-precision values
      target/arm/cpu.h: add additional float_status flags
      target/arm/helper: pass explicit fpst to set_rmode
      arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
      arm/translate-a64: handle_3same_64 comment fix
      arm/translate-a64: initial decode for simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
      arm/translate-a64: add FP16 x2 ops for simd_indexed
      arm/translate-a64: initial decode for simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
      arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
      arm/helper.c: re-factor recpe and add recepe_f16
      arm/translate-a64: add FP16 FRECPE
      arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
      arm/helper.c: re-factor rsqrte and add rsqrte_f16
      arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FMOV to simd_mod_imm
      arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
      arm/translate-a64: implement simd_scalar_three_reg_same_fp16
      arm/translate-a64: add all single op FP16 to handle_fp_1src_half

Alistair Francis (2):
      hw: register: Run post_write hook on reset
      MAINTAINERS: Update my email address

Corey Minyard (2):
      i2c: Fix some brace style issues
      i2c: Move the bus class to i2c.h

Francisco Iglesias (2):
      xilinx_spips: Enable only two slaves when reading/writing with stripe
      xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands

Linus Walleij (3):
      hw/i2c-ddc: Do not fail writes
      hw/sii9022: Add support for Silicon Image SII9022
      arm/vexpress: Add proper display connector emulation

Peter Maydell (2):
      target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
      linux-user: Report AArch64 FP16 support via hwcap bits

 hw/display/Makefile.objs        |    1 +
 include/exec/helper-head.h      |    3 +
 include/fpu/softfloat.h         |   18 +-
 include/hw/i2c/i2c.h            |   23 +-
 include/hw/register.h           |    6 +-
 target/arm/cpu.h                |   34 +-
 target/arm/helper-a64.h         |   33 +
 target/arm/helper.h             |   14 +-
 hw/arm/vexpress.c               |    6 +-
 hw/core/register.c              |    8 +
 hw/display/sii9022.c            |  191 ++++++
 hw/i2c/core.c                   |   18 -
 hw/i2c/i2c-ddc.c                |    4 +-
 hw/ssi/xilinx_spips.c           |   43 +-
 linux-user/elfload.c            |    2 +
 target/arm/cpu64.c              |    1 +
 target/arm/helper-a64.c         |  269 +++++++++
 target/arm/helper.c             |  481 ++++++++-------
 target/arm/translate-a64.c      | 1266 +++++++++++++++++++++++++++++++++------
 target/arm/translate.c          |   12 +-
 MAINTAINERS                     |   12 +-
 default-configs/arm-softmmu.mak |    2 +
 hw/display/trace-events         |    5 +
 23 files changed, 1981 insertions(+), 471 deletions(-)
 create mode 100644 hw/display/sii9022.c

Comments

no-reply@patchew.org March 1, 2018, 1 p.m. UTC | #1 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180301112403.12487-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/42] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   5116c331c6..2963d78204  master     -> master
 * [new tag]               patchew/20180301112403.12487-1-peter.maydell@linaro.org -> patchew/20180301112403.12487-1-peter.maydell@linaro.org
Switched to a new branch 'test'
b8d820da8e MAINTAINERS: Update my email address
fafefeede8 linux-user: Report AArch64 FP16 support via hwcap bits
1e47f0c8d0 target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
a1d78601d3 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
ef1aeecd4b arm/translate-a64: implement simd_scalar_three_reg_same_fp16
6f2836d485 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
a35291f349 arm/translate-a64: add FP16 FMOV to simd_mod_imm
0a27cbb4ed arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
0a441b7da4 arm/helper.c: re-factor rsqrte and add rsqrte_f16
da2e0fc44a arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
4cef2369d2 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
1b4f1ab980 arm/translate-a64: add FP16 FRECPE
73a9e97036 arm/helper.c: re-factor recpe and add recepe_f16
90ba4bd8c2 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
73fd85ed2b arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
f19cc5a183 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
65f396e589 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
0e24214ab5 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
f196ce6fe6 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
34d06595e7 arm/translate-a64: add FP16 x2 ops for simd_indexed
1cbb0530d6 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
2784d82ed6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
d384cdd281 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
8f8a6ce448 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
126916bc89 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
4173362d9a arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
933cd48012 arm/translate-a64: initial decode for simd_three_reg_same_fp16
b990db46a4 arm/translate-a64: handle_3same_64 comment fix
d35bfc6ddd arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
f7b5043d8e target/arm/helper: pass explicit fpst to set_rmode
f4942cc7c8 target/arm/cpu.h: add additional float_status flags
8f2a0f5575 target/arm/cpu.h: update comment for half-precision values
3059f5906d target/arm/cpu64: introduce ARM_V8_FP16 feature bit
aac25f27be include/exec/helper-head.h: support f16 in helper calls
5998ce1e24 arm/vexpress: Add proper display connector emulation
cd734131b2 hw/sii9022: Add support for Silicon Image SII9022
94b945c24d hw/i2c-ddc: Do not fail writes
fb66477d35 i2c: Move the bus class to i2c.h
96b6d99806 i2c: Fix some brace style issues
6fdd76003e xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
0a63d14eaa xilinx_spips: Enable only two slaves when reading/writing with stripe
3a5412277e hw: register: Run post_write hook on reset

=== OUTPUT BEGIN ===
Checking PATCH 1/42: hw: register: Run post_write hook on reset...
Checking PATCH 2/42: xilinx_spips: Enable only two slaves when reading/writing with stripe...
Checking PATCH 3/42: xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands...
Checking PATCH 4/42: i2c: Fix some brace style issues...
Checking PATCH 5/42: i2c: Move the bus class to i2c.h...
Checking PATCH 6/42: hw/i2c-ddc: Do not fail writes...
Checking PATCH 7/42: hw/sii9022: Add support for Silicon Image SII9022...
Checking PATCH 8/42: arm/vexpress: Add proper display connector emulation...
Checking PATCH 9/42: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 10/42: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 11/42: target/arm/cpu.h: update comment for half-precision values...
Checking PATCH 12/42: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 13/42: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 14/42: arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)...
Checking PATCH 15/42: arm/translate-a64: handle_3same_64 comment fix...
Checking PATCH 16/42: arm/translate-a64: initial decode for simd_three_reg_same_fp16...
Checking PATCH 17/42: arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16...
Checking PATCH 18/42: arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16...
Checking PATCH 19/42: arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16...
Checking PATCH 20/42: arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16...
Checking PATCH 21/42: arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16...
Checking PATCH 22/42: arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed...
Checking PATCH 23/42: arm/translate-a64: add FP16 x2 ops for simd_indexed...
Checking PATCH 24/42: arm/translate-a64: initial decode for simd_two_reg_misc_fp16...
Checking PATCH 25/42: arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16...
Checking PATCH 26/42: arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16...
Checking PATCH 27/42: arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16...
Checking PATCH 28/42: arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16...
ERROR: space prohibited before that close parenthesis ')'
#28: FILE: target/arm/helper.c:11305:
+FLOAT_CONVS(si, h, 16, )

total: 1 errors, 0 warnings, 208 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 29/42: arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16...
Checking PATCH 30/42: arm/helper.c: re-factor recpe and add recepe_f16...
Checking PATCH 31/42: arm/translate-a64: add FP16 FRECPE...
Checking PATCH 32/42: arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16...
Checking PATCH 33/42: arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16...
Checking PATCH 34/42: arm/helper.c: re-factor rsqrte and add rsqrte_f16...
Checking PATCH 35/42: arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16...
Checking PATCH 36/42: arm/translate-a64: add FP16 FMOV to simd_mod_imm...
Checking PATCH 37/42: arm/translate-a64: add all FP16 ops in simd_scalar_pairwise...
Checking PATCH 38/42: arm/translate-a64: implement simd_scalar_three_reg_same_fp16...
Checking PATCH 39/42: arm/translate-a64: add all single op FP16 to handle_fp_1src_half...
Checking PATCH 40/42: target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU...
Checking PATCH 41/42: linux-user: Report AArch64 FP16 support via hwcap bits...
Checking PATCH 42/42: MAINTAINERS: Update my email address...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
no-reply@patchew.org March 1, 2018, 1:01 p.m. UTC | #2 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180301112403.12487-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/42] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   5116c331c6..2963d78204  master     -> master
 * [new tag]               patchew/20180301112403.12487-1-peter.maydell@linaro.org -> patchew/20180301112403.12487-1-peter.maydell@linaro.org
Switched to a new branch 'test'
b8d820da8e MAINTAINERS: Update my email address
fafefeede8 linux-user: Report AArch64 FP16 support via hwcap bits
1e47f0c8d0 target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
a1d78601d3 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
ef1aeecd4b arm/translate-a64: implement simd_scalar_three_reg_same_fp16
6f2836d485 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
a35291f349 arm/translate-a64: add FP16 FMOV to simd_mod_imm
0a27cbb4ed arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
0a441b7da4 arm/helper.c: re-factor rsqrte and add rsqrte_f16
da2e0fc44a arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
4cef2369d2 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
1b4f1ab980 arm/translate-a64: add FP16 FRECPE
73a9e97036 arm/helper.c: re-factor recpe and add recepe_f16
90ba4bd8c2 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
73fd85ed2b arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
f19cc5a183 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
65f396e589 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
0e24214ab5 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
f196ce6fe6 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
34d06595e7 arm/translate-a64: add FP16 x2 ops for simd_indexed
1cbb0530d6 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
2784d82ed6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
d384cdd281 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
8f8a6ce448 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
126916bc89 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
4173362d9a arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
933cd48012 arm/translate-a64: initial decode for simd_three_reg_same_fp16
b990db46a4 arm/translate-a64: handle_3same_64 comment fix
d35bfc6ddd arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
f7b5043d8e target/arm/helper: pass explicit fpst to set_rmode
f4942cc7c8 target/arm/cpu.h: add additional float_status flags
8f2a0f5575 target/arm/cpu.h: update comment for half-precision values
3059f5906d target/arm/cpu64: introduce ARM_V8_FP16 feature bit
aac25f27be include/exec/helper-head.h: support f16 in helper calls
5998ce1e24 arm/vexpress: Add proper display connector emulation
cd734131b2 hw/sii9022: Add support for Silicon Image SII9022
94b945c24d hw/i2c-ddc: Do not fail writes
fb66477d35 i2c: Move the bus class to i2c.h
96b6d99806 i2c: Fix some brace style issues
6fdd76003e xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
0a63d14eaa xilinx_spips: Enable only two slaves when reading/writing with stripe
3a5412277e hw: register: Run post_write hook on reset

=== OUTPUT BEGIN ===
Checking PATCH 1/42: hw: register: Run post_write hook on reset...
Checking PATCH 2/42: xilinx_spips: Enable only two slaves when reading/writing with stripe...
Checking PATCH 3/42: xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands...
Checking PATCH 4/42: i2c: Fix some brace style issues...
Checking PATCH 5/42: i2c: Move the bus class to i2c.h...
Checking PATCH 6/42: hw/i2c-ddc: Do not fail writes...
Checking PATCH 7/42: hw/sii9022: Add support for Silicon Image SII9022...
Checking PATCH 8/42: arm/vexpress: Add proper display connector emulation...
Checking PATCH 9/42: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 10/42: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 11/42: target/arm/cpu.h: update comment for half-precision values...
Checking PATCH 12/42: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 13/42: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 14/42: arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)...
Checking PATCH 15/42: arm/translate-a64: handle_3same_64 comment fix...
Checking PATCH 16/42: arm/translate-a64: initial decode for simd_three_reg_same_fp16...
Checking PATCH 17/42: arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16...
Checking PATCH 18/42: arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16...
Checking PATCH 19/42: arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16...
Checking PATCH 20/42: arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16...
Checking PATCH 21/42: arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16...
Checking PATCH 22/42: arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed...
Checking PATCH 23/42: arm/translate-a64: add FP16 x2 ops for simd_indexed...
Checking PATCH 24/42: arm/translate-a64: initial decode for simd_two_reg_misc_fp16...
Checking PATCH 25/42: arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16...
Checking PATCH 26/42: arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16...
Checking PATCH 27/42: arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16...
Checking PATCH 28/42: arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16...
ERROR: space prohibited before that close parenthesis ')'
#28: FILE: target/arm/helper.c:11305:
+FLOAT_CONVS(si, h, 16, )

total: 1 errors, 0 warnings, 208 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 29/42: arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16...
Checking PATCH 30/42: arm/helper.c: re-factor recpe and add recepe_f16...
Checking PATCH 31/42: arm/translate-a64: add FP16 FRECPE...
Checking PATCH 32/42: arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16...
Checking PATCH 33/42: arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16...
Checking PATCH 34/42: arm/helper.c: re-factor rsqrte and add rsqrte_f16...
Checking PATCH 35/42: arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16...
Checking PATCH 36/42: arm/translate-a64: add FP16 FMOV to simd_mod_imm...
Checking PATCH 37/42: arm/translate-a64: add all FP16 ops in simd_scalar_pairwise...
Checking PATCH 38/42: arm/translate-a64: implement simd_scalar_three_reg_same_fp16...
Checking PATCH 39/42: arm/translate-a64: add all single op FP16 to handle_fp_1src_half...
Checking PATCH 40/42: target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU...
Checking PATCH 41/42: linux-user: Report AArch64 FP16 support via hwcap bits...
Checking PATCH 42/42: MAINTAINERS: Update my email address...
=== OUTPUT END ===

Test command exited with code: 1


---
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Peter Maydell March 1, 2018, 2:45 p.m. UTC | #3 
On 1 March 2018 at 13:00,  <no-reply@patchew.org> wrote:
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Message-id: 20180301112403.12487-1-peter.maydell@linaro.org
> Subject: [Qemu-devel] [PULL 00/42] target-arm queue

Fam -- any idea why patchew sent two checkpatch-issues emails for
this patchset ? The Message-IDs are:
<151990924540.1290.18181910407458585370@bdbb90650ae5>
<151990926291.1290.9842237231347453757@bdbb90650ae5>

thanks
-- PMM
Peter Maydell March 1, 2018, 5:08 p.m. UTC | #4 
On 1 March 2018 at 11:23, Peter Maydell <peter.maydell@linaro.org> wrote:
> Arm queue -- I have more stuff pending but I prefer to push
> this first lot out and keep the pull below 50 patches.
> Most of this is Alex's FP16 support work.
>
> -- PMM
>
>
> The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)
>
> are available in the Git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301
>
> for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:
>
>   MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * update MAINTAINERS for Alistair's new email address
>  * add Arm v8.2 FP16 arithmetic extension for linux-user
>  * implement display connector emulation for vexpress board
>  * xilinx_spips: Enable only two slaves when reading/writing with stripe
>  * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
>  * hw: register: Run post_write hook on reset
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM
Fam Zheng March 2, 2018, 12:52 a.m. UTC | #5 
On Thu, Mar 1, 2018 at 10:45 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 1 March 2018 at 13:00,  <no-reply@patchew.org> wrote:
>> Hi,
>>
>> This series seems to have some coding style problems. See output below for
>> more information:
>>
>> Type: series
>> Message-id: 20180301112403.12487-1-peter.maydell@linaro.org
>> Subject: [Qemu-devel] [PULL 00/42] target-arm queue
>
> Fam -- any idea why patchew sent two checkpatch-issues emails for
> this patchset ? The Message-IDs are:
> <151990924540.1290.18181910407458585370@bdbb90650ae5>
> <151990926291.1290.9842237231347453757@bdbb90650ae5>

A bug in patchew. The server dispatched the checkpatch task to two testers
when they asked for more work to do. One of them shouldn't happen.
I've worked around this in the config
(filtering the task into only one tester) now.

I created an issue.

https://github.com/patchew-project/patchew/issues/63

Fam