From patchwork Tue Feb 13 04:07:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 872584 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="j9yA8RV7"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zgTx90Sxlz9sPk for ; Tue, 13 Feb 2018 15:25:49 +1100 (AEDT) Received: from localhost ([::1]:37650 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1elSA7-0006f8-2K for incoming@patchwork.ozlabs.org; Mon, 12 Feb 2018 23:25:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1elRu4-0001Df-R4 for qemu-devel@nongnu.org; Mon, 12 Feb 2018 23:09:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1elRu3-0007qM-Kx for qemu-devel@nongnu.org; Mon, 12 Feb 2018 23:09:12 -0500 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:37883) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1elRu3-0007qE-FM; Mon, 12 Feb 2018 23:09:11 -0500 Received: by mail-qk0-x241.google.com with SMTP id c128so21065666qkb.4; Mon, 12 Feb 2018 20:09:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6I0eLeCnx4eW7xx/FEABgkNDEMBh/XvlA3Ez3K+OV/Q=; b=j9yA8RV7Ko/lrpTp31+xiCGBcv6NNSvB93jDgLiFaRcJmZt9uChe2llie4InDlrTBO 1oXCsPTA3oVSxcLj6BTPxRKfj59jg6UkKbTshZLc1TiydtL9gruCBbrzr590P8Z15Jwq wjrqIVFJpIRRJNwbymqsqX4I0w9fUou+NCdmeXZFouTxDNM3qI0kF7ozHthlgxE8FyOv RpwxQiyS8kMC1rVMu1Q0ala/TXCitISp4RsKlPkyOkGvOiqAqHpdtwkvFCNXXegCZqAA K/v8Y2cuL4KLVsbrDyZ9tiNiBXqZAY8nsxyxOXfe9jQk/rUP+Rv4dt3OdGcVRD3ebugw 5OYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6I0eLeCnx4eW7xx/FEABgkNDEMBh/XvlA3Ez3K+OV/Q=; b=cuVo1W+MfC1zgpR7DY+ak3PBqecPT52HNqvkJnBCvMcctQBXqEU+q6sJlMLFDOwM3K DbnvG6vTqmcYnP9sxCo0m7koxCEMMIRKrCZDvATH3BKC63DyEQZfp/PFNXchaFP7+/HI Peo5EkNNOs3tBMXKtZKtaRyIOm/PFY2/PrMtmz5/l0qJ/vl25QpgT1c9A1QyLlgGwLsq 7r+UGlExfOD52OpDNcObnhAjaidqSJuShHmaRIG1cykqs8X2q9j8/2a+2zJJ+JxjKCYd bFdt8V52mlPOAhg3VUk6j5kSNOxWAiC69lN5J+T9VqSxTXWcm0xC+y8xYhC8+t6lcOz2 +m3g== X-Gm-Message-State: APf1xPCGYhzjRjKyzTTdcji9A9cAZppf1TLJscpemzExGF8G+2G8GFWX uLDZ9380Oo/iHFTt0o38wJ0GoEAX X-Google-Smtp-Source: AH8x226YPWcFKjrc/UfnCY21LH/tMUM5unn/SKDIRnxqsRtwD2HU6EESNe2AHRvrA4xcw/iRrRR93A== X-Received: by 10.55.24.34 with SMTP id j34mr17325123qkh.294.1518494950894; Mon, 12 Feb 2018 20:09:10 -0800 (PST) Received: from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id q2sm7350435qki.10.2018.02.12.20.09.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Feb 2018 20:09:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini Date: Tue, 13 Feb 2018 01:07:55 -0300 Message-Id: <20180213040809.26021-17-f4bug@amsat.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180213040809.26021-1-f4bug@amsat.org> References: <20180213040809.26021-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v13 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Peter Maydell , Fam Zheng , qemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , "open list:Xilinx Zynq" , "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" checking Xilinx datasheet "UG585" (v1.12.1) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/xilinx_zynq.c | 53 ++++++++++++++++++++++++++++------------------------ tests/sdhci-test.c | 5 +++++ 2 files changed, 34 insertions(+), 24 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 1836a4ed45..0f76333770 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -61,6 +61,8 @@ static const int dma_irqs[8] = { #define SLCR_XILINX_UNLOCK_KEY 0xdf0d #define SLCR_XILINX_LOCK_KEY 0x767b +#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ + #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ extract32((x), 12, 4) << 16) @@ -165,10 +167,8 @@ static void zynq_init(MachineState *machine) MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ext_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); - DeviceState *dev, *carddev; + DeviceState *dev; SysBusDevice *busdev; - DriveInfo *di; - BlockBackend *blk; qemu_irq pic[64]; int n; @@ -247,27 +247,32 @@ static void zynq_init(MachineState *machine) gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); - dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); - - di = drive_get_next(IF_SD); - blk = di ? blk_by_legacy_dinfo(di) : NULL; - carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); - qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); - object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); - - dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); - - di = drive_get_next(IF_SD); - blk = di ? blk_by_legacy_dinfo(di) : NULL; - carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); - qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); - object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); + for (n = 0; n < 2; n++) { + int hci_irq = n ? 79 : 56; + hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; + DriveInfo *di; + BlockBackend *blk; + DeviceState *carddev; + + /* Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + * - SDIO Specification Version 2.0 + * - MMC Specification Version 3.31 + */ + dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); + + di = drive_get_next(IF_SD); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, "realized", + &error_fatal); + } dev = qdev_create(NULL, TYPE_ZYNQ_XADC); qdev_init_nofail(dev); diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index 24feea744a..898c43ff4f 100644 --- a/tests/sdhci-test.c +++ b/tests/sdhci-test.c @@ -41,6 +41,11 @@ static const struct sdhci_t { /* Exynos4210 */ { "arm", "smdkc210", {0x12510000, 2, 0, {1, 0x5e80080} } }, + + /* Zynq-7000 */ + { "arm", "xilinx-zynq-a9", /* Datasheet: UG585 (v1.12.1) */ + {0xe0100000, 2, 0, {1, 0x69ec0080} } }, + }; typedef struct QSDHCI {