From patchwork Sat Feb 10 23:05:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871713 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="CoWOskR6"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zf6yD2qQqz9sDB for ; Sun, 11 Feb 2018 10:07:00 +1100 (AEDT) Received: from localhost ([::1]:45806 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeEU-00070S-D0 for incoming@patchwork.ozlabs.org; Sat, 10 Feb 2018 18:06:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ekeDE-0006VW-Ba for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ekeDB-00083y-QS for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:40 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:40696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ekeDB-000833-Jv for qemu-devel@nongnu.org; Sat, 10 Feb 2018 18:05:37 -0500 Received: by mail-pg0-x244.google.com with SMTP id g2so5473717pgn.7 for ; Sat, 10 Feb 2018 15:05:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=db7o6VMgdo08ugsOkXJ4Br6qKJbdNpL9zH2Gp3+8vaw=; b=CoWOskR625v8onaamWjTOW47R45NzFqwOH/2bNk7Mgi1DcD7yMItWxnXtQGYPdB/rO qkNVbEeesIYZ6tEk9xQjHORB84mYNjL9pzCe7pFWhS/AsGkQNGQrWG1jzjU9PJbXejKB BGbZyKfVU+oaTvE18Z31xgBQojG5EUo3nW7v0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=db7o6VMgdo08ugsOkXJ4Br6qKJbdNpL9zH2Gp3+8vaw=; b=hT99sFP2yMXdVA4z9AndTnQkFHgzkDCI7uCsNkaFcKUNy7uXV6cfkBEX2h89mbTVv0 iXJ87Hgwk3SOhlx+ocSB3p/qivMAV476szdFTqyuXqSYQlNzUoYrlbawSzk2Y7df1sv6 s0i870Z6IzJDwS5x5A05shttvh4O3kdXn4bslCzd+Lxi76DlouC3dgD4OL+uHEQXMN0U PKJCmpmJfayevaRTYbYB8uFIWyYnzA6MCSDm1/0YAQIzqE5TlAGkp7a/rdCRe+tM/8yL mLw1sqAODFFD8YLPsXCXyGpPLNZy368Wq6nteLbeiWGZvy/9p0SGjaGATo8a1cst1QYp H+Nw== X-Gm-Message-State: APf1xPBdlpRfHiKd7Bgx5WQLTHM/Ml+JHU3rRidpnQIVL+EpzpHwN65l hdY1/iYetxXxVwNyGqT/pUBUtBLoKSs= X-Google-Smtp-Source: AH8x224akJm/UDgpo8uqmBHhROyHQNO1IJNPB0DHCnoa/uHLrN0zgLEdHMOksVDeXUm8fZ8K6Ptdtw== X-Received: by 10.99.110.3 with SMTP id j3mr5883490pgc.85.1518303936259; Sat, 10 Feb 2018 15:05:36 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id w10sm14122374pgr.57.2018.02.10.15.05.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Feb 2018 15:05:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 10 Feb 2018 15:05:27 -0800 Message-Id: <20180210230530.8421-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210230530.8421-1-richard.henderson@linaro.org> References: <20180210230530.8421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 2/5] target/arm: Enforce FP access to FPCR/FPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 35 ++++++++++++++++++----------------- target/arm/helper.c | 6 ++++-- target/arm/translate-a64.c | 3 +++ 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 521444a5a1..e966a57f8a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1714,7 +1714,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) } /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [15..8] indicate what behaviour + * special-behaviour cp reg and bits [11..8] indicate what behaviour * it has. Otherwise it is a simple cp reg, where CONST indicates that * TCG can assume the value to be constant (ie load at translate time) * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END @@ -1735,24 +1735,25 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. */ -#define ARM_CP_SPECIAL 1 -#define ARM_CP_CONST 2 -#define ARM_CP_64BIT 4 -#define ARM_CP_SUPPRESS_TB_END 8 -#define ARM_CP_OVERRIDE 16 -#define ARM_CP_ALIAS 32 -#define ARM_CP_IO 64 -#define ARM_CP_NO_RAW 128 -#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) -#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_SPECIAL 0x0001 +#define ARM_CP_CONST 0x0002 +#define ARM_CP_64BIT 0x0004 +#define ARM_CP_SUPPRESS_TB_END 0x0008 +#define ARM_CP_OVERRIDE 0x0010 +#define ARM_CP_ALIAS 0x0020 +#define ARM_CP_IO 0x0040 +#define ARM_CP_NO_RAW 0x0080 +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) +#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_FPU 0x1000 /* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xffff +#define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0xff +#define ARM_CP_FLAG_MASK 0x10ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index 4b102ec356..d41fb8371f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3356,10 +3356,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, { .name = "FPCR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, - .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, + .access = PL0_RW, .type = ARM_CP_FPU, + .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, { .name = "FPSR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, - .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, + .access = PL0_RW, .type = ARM_CP_FPU, + .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, .access = PL0_R, .type = ARM_CP_NO_RAW, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fb1a4cb532..89f50558a7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1631,6 +1631,9 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, default: break; } + if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + return; + } if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start();