From patchwork Fri Jan 19 14:17:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 863564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="DefZIc8r"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zNNRM3VTXz9s7G for ; Sat, 20 Jan 2018 01:26:07 +1100 (AEDT) Received: from localhost ([::1]:52077 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecXcL-0003sf-Ej for incoming@patchwork.ozlabs.org; Fri, 19 Jan 2018 09:26:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58692) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecXTz-0005Dx-6M for qemu-devel@nongnu.org; Fri, 19 Jan 2018 09:17:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecXTy-0004Aq-Cg for qemu-devel@nongnu.org; Fri, 19 Jan 2018 09:17:27 -0500 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:45641) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecXTy-000498-6S for qemu-devel@nongnu.org; Fri, 19 Jan 2018 09:17:26 -0500 Received: by mail-wr0-x241.google.com with SMTP id 16so1700345wry.12 for ; Fri, 19 Jan 2018 06:17:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iQ1FLKmYb4BjFce8j24OXUKRD4+hEekWhEWExhcW0Ys=; b=DefZIc8ruBKX1rFOb3FoknEgzvbsJrZ93TpDZIBiyVPQpMVIKpMwGFhbcbcqWDHJSf dWndMYn6CRGw2E67jzWMggBVZ16qms8XZhW92hnZUMOLubzWG23GAVPjxvE3fz6rnbj4 QxZnfhYhHPk5Ky0X+Q7g8gnWQsE31raCrQON4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iQ1FLKmYb4BjFce8j24OXUKRD4+hEekWhEWExhcW0Ys=; b=AT7bstWM/R7VU7V64j0GaHS93ld4nPCUyDJzjVMHU1Nu7QTRnF8aP33fUpPIAr3+kR i5P2sB9hr7nKazDI4tum8jS9BbLUN9gpSmu+EAfFDFLHX6hgahzJIbInD3bXsrEYqrgV Me3fP7li/aXWLENmekvYkQeGFjZdTf1agXxZGtT44eAJVc+gDoEl779ZOHEEN4rTxOR3 xFvXB9KLmyfxzWNrQONPx6WjFJZUT+3t6xz5J5MDgZlV+pXQs3dzZNQiS1HyP1KyZ6iA IevQyOHw/Ll52nP5rWupsopmBpCc9Wldg301TaRqFyNH21pAy2qyGcv0dFkKkkxTAdhF v1fQ== X-Gm-Message-State: AKwxyteDvQCvWT0D2b3Z1nUcK0U5LF16l9eNV/BF1LQWYVaVTBNJnqp2 OeC76j46WYbSpneRiGvub31oWqqEALY= X-Google-Smtp-Source: ACJfBotqYkSr8Y9CvXO6IGxF2JElZhWV1qG4kHETBsyoSTMUb6uWwfhnXzalKkOi8OGbof9zmXTuag== X-Received: by 10.223.166.248 with SMTP id t111mr10371671wrc.248.1516371444996; Fri, 19 Jan 2018 06:17:24 -0800 (PST) Received: from localhost.localdomain ([160.170.62.40]) by smtp.gmail.com with ESMTPSA id m45sm6877266wrf.75.2018.01.19.06.17.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 06:17:24 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Fri, 19 Jan 2018 14:17:07 +0000 Message-Id: <20180119141707.11733-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119141707.11733-1-ard.biesheuvel@linaro.org> References: <20180119141707.11733-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v3 4/4] target/arm: enable user-mode SHA-3, SM3 and SHA-512 instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the new ARMv8.2 SHA-3, SM3 and SHA-512 instructions to AArch64 user mode emulation. Signed-off-by: Ard Biesheuvel --- linux-user/elfload.c | 18 ++++++++++++++++++ target/arm/cpu64.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c373..5d5aa26d2710 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,21 @@ enum { ARM_HWCAP_A64_SHA1 = 1 << 5, ARM_HWCAP_A64_SHA2 = 1 << 6, ARM_HWCAP_A64_CRC32 = 1 << 7, + ARM_HWCAP_A64_ATOMICS = 1 << 8, + ARM_HWCAP_A64_FPHP = 1 << 9, + ARM_HWCAP_A64_ASIMDHP = 1 << 10, + ARM_HWCAP_A64_CPUID = 1 << 11, + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, + ARM_HWCAP_A64_JSCVT = 1 << 13, + ARM_HWCAP_A64_FCMA = 1 << 14, + ARM_HWCAP_A64_LRCPC = 1 << 15, + ARM_HWCAP_A64_DCPOP = 1 << 16, + ARM_HWCAP_A64_SHA3 = 1 << 17, + ARM_HWCAP_A64_SM3 = 1 << 18, + ARM_HWCAP_A64_SM4 = 1 << 19, + ARM_HWCAP_A64_ASIMDDP = 1 << 20, + ARM_HWCAP_A64_SHA512 = 1 << 21, + ARM_HWCAP_A64_SVE = 1 << 22, }; #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +547,9 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); #undef GET_FEATURE return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6ed4..56d50ba57194 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -224,6 +224,9 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */