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X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v5 07/31] sdhci: Fix 64-bit ADMA2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Prasad J Pandit , =?utf-8?q?Gr=C3=A9gory_Estrade?= , Peter Crosthwaite , qemu-devel@nongnu.org, Krzysztof Kozlowski , Jean-Christophe Dubois , Sai Pavan Boddu , qemu-arm@nongnu.org, Clement Deschamps , Andrew Baumann , Eduardo Habkost Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sai Pavan Boddu The 64-bit ADMA address is not converted to the cpu endianes correctly. This patch fixes the issue and uses a valid mask for the attribute data. Signed-off-by: Sai Pavan Boddu [AF: Re-write commit message] Reviewed-by: Alistair Francis --- hw/sd/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 88052fcc44..83b027a3b6 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -623,8 +623,8 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) dscr->length = le16_to_cpu(dscr->length); dma_memory_read(&s->dma_as, entry_addr + 4, (uint8_t *)(&dscr->addr), 8); - dscr->attr = le64_to_cpu(dscr->attr); - dscr->attr &= 0xfffffff8; + dscr->addr = le64_to_cpu(dscr->addr); + dscr->attr &= (uint8_t) ~0xC0; dscr->incr = 12; break; }