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X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v5 02/31] sdhci: add basic Spec v1 capabilities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Prasad J Pandit , =?utf-8?q?Gr=C3=A9gory_Estrade?= , qemu-devel@nongnu.org, Peter Crosthwaite , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Krzysztof Kozlowski , Jean-Christophe Dubois , Sai Pavan Boddu , qemu-arm@nongnu.org, Clement Deschamps , Andrew Baumann , Eduardo Habkost Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-internal.h | 22 ++++++++++++++++++- include/hw/sd/sdhci.h | 6 ++++++ hw/sd/sdhci.c | 58 ++++++++++++++++++++++++++++++++++++-------------- 3 files changed, 69 insertions(+), 17 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index cf4a055159..6944fcaf00 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -86,6 +86,9 @@ FIELD(SDHC_PRNSTS, WRITE_PROTECT, 19, 1); /* R/W Host control Register 0x0 */ #define SDHC_HOSTCTL 0x28 +FIELD(SDHC_HOSTCTL, LED_CTRL, 0, 1); +FIELD(SDHC_HOSTCTL, DATATRANSFERWIDTH, 1, 1); /* SD mode only */ +FIELD(SDHC_HOSTCTL, HIGH_SPEED, 2, 1); #define SDHC_CTRL_DMA_CHECK_MASK 0x18 #define SDHC_CTRL_SDMA 0x00 #define SDHC_CTRL_ADMA1_32 0x08 @@ -96,6 +99,7 @@ FIELD(SDHC_PRNSTS, WRITE_PROTECT, 19, 1); /* R/W Power Control Register 0x0 */ #define SDHC_PWRCON 0x29 #define SDHC_POWER_ON (1 << 0) +FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3); /* R/W Block Gap Control Register 0x0 */ #define SDHC_BLKGAP 0x2A @@ -118,6 +122,7 @@ FIELD(SDHC_PRNSTS, WRITE_PROTECT, 19, 1); /* R/W Timeout Control Register 0x0 */ #define SDHC_TIMEOUTCON 0x2E +FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); /* R/W Software Reset Register 0x0 */ #define SDHC_SWRST 0x2F @@ -174,17 +179,32 @@ FIELD(SDHC_PRNSTS, WRITE_PROTECT, 19, 1); /* ROC Auto CMD12 error status register 0x0 */ #define SDHC_ACMD12ERRSTS 0x3C +FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1); +FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1); +FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1); /* HWInit Capabilities Register 0x05E80080 */ #define SDHC_CAPAB 0x40 -#define SDHC_CAN_DO_DMA 0x00400000 #define SDHC_CAN_DO_ADMA2 0x00080000 #define SDHC_CAN_DO_ADMA1 0x00100000 #define SDHC_64_BIT_BUS_SUPPORT (1 << 28) #define SDHC_CAPAB_BLOCKSIZE(x) (((x) >> 16) & 0x3) +FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); +FIELD(SDHC_CAPAB, TOUNIT, 7, 1); +FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); +FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2); +FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1); +FIELD(SDHC_CAPAB, SDMA, 22, 1); +FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1); +FIELD(SDHC_CAPAB, V33, 24, 1); +FIELD(SDHC_CAPAB, V30, 25, 1); +FIELD(SDHC_CAPAB, V18, 26, 1); /* HWInit Maximum Current Capabilities Register 0x0 */ #define SDHC_MAXCURR 0x48 +FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8); +FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8); +FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8); /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */ #define SDHC_FEAER 0x50 diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index ddd5040410..266030dc8d 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -102,6 +102,12 @@ typedef struct SDHCIState { /* Configurable properties */ bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ uint8_t spec_version; + struct { + bool suspend; + bool high_speed; + bool sdma; + bool v33, v30, v18; + } cap; } SDHCIState; #define TYPE_PCI_SDHCI "sdhci-pci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index cd4a8efdd7..e7dbab2fdc 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -44,12 +44,6 @@ * 0 - not supported, 1 - supported, other - prohibited. */ #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ -#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ -#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ -#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ -#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ -#define SDHC_CAPAB_SDMA 1ul /* SDMA support */ -#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ /* Maximum host controller R/W buffers size @@ -63,9 +57,7 @@ #define SDHC_CAPAB_TOCLKFREQ 52ul /* Now check all parameters and calculate CAPABILITIES REGISTER value */ -#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ - SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ - SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ +#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 || \ SDHC_CAPAB_TOUNIT > 1 #error Capabilities features can have value 0 or 1 only! #endif @@ -90,16 +82,33 @@ #endif #define SDHC_CAPAB_REG_DEFAULT \ - ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ - (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ - (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ - (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ + ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_ADMA1 << 20) | \ (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ (SDHC_CAPAB_TOCLKFREQ)) #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) +static void sdhci_init_capareg(SDHCIState *s, Error **errp) +{ + uint64_t capareg = 0; + + switch (s->spec_version) { + case 1: + capareg = FIELD_DP64(capareg, SDHC_CAPAB, HIGHSPEED, s->cap.high_speed); + capareg = FIELD_DP64(capareg, SDHC_CAPAB, SDMA, s->cap.sdma); + capareg = FIELD_DP64(capareg, SDHC_CAPAB, SUSPRESUME, s->cap.suspend); + capareg = FIELD_DP64(capareg, SDHC_CAPAB, V33, s->cap.v33); + capareg = FIELD_DP64(capareg, SDHC_CAPAB, V30, s->cap.v30); + capareg = FIELD_DP64(capareg, SDHC_CAPAB, V18, s->cap.v18); + break; + + default: + error_setg(errp, "Unsupported spec version: %u", s->spec_version); + } + s->capareg = capareg; +} + static uint8_t sdhci_slotint(SDHCIState *s) { return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || @@ -1032,7 +1041,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) case SDHC_TRNMOD: /* DMA can be enabled only if it is supported as indicated by * capabilities register */ - if (!(s->capareg & SDHC_CAN_DO_DMA)) { + if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { value &= ~SDHC_TRNS_DMA; } MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); @@ -1186,6 +1195,10 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) return; } s->version = (SDHC_HCVER_VENDOR << 8) | (s->spec_version - 1); + + if (s->capareg == UINT64_MAX) { + sdhci_init_capareg(s, errp); + } } static void sdhci_initfn(SDHCIState *s) @@ -1305,8 +1318,21 @@ const VMStateDescription sdhci_vmstate = { * specific host controller implementation */ static Property sdhci_properties[] = { DEFINE_PROP_UINT8("sd-spec-version", SDHCIState, spec_version, 2), - DEFINE_PROP_UINT64("capareg", SDHCIState, capareg, - SDHC_CAPAB_REG_DEFAULT), + + /* DMA */ + DEFINE_PROP_BOOL("sdma", SDHCIState, cap.sdma, true), + /* Suspend/resume support */ + DEFINE_PROP_BOOL("suspend", SDHCIState, cap.suspend, false), + /* High speed support */ + DEFINE_PROP_BOOL("high-speed", SDHCIState, cap.high_speed, true), + /* Voltage support 3.3/3.0/1.8V */ + DEFINE_PROP_BOOL("3v3", SDHCIState, cap.v33, true), + DEFINE_PROP_BOOL("3v0", SDHCIState, cap.v30, false), + DEFINE_PROP_BOOL("1v8", SDHCIState, cap.v18, false), + + /* capareg: deprecated */ + DEFINE_PROP_UINT64("capareg", SDHCIState, capareg, UINT64_MAX), + DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0), DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, false),