From patchwork Thu Jan 4 01:29:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 855335 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zBrGH4bl2z9s7n for ; Thu, 4 Jan 2018 12:45:11 +1100 (AEDT) Received: from localhost ([::1]:44852 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eWuaj-0003lh-M9 for incoming@patchwork.ozlabs.org; Wed, 03 Jan 2018 20:45:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eWuLW-0000vH-TP for qemu-devel@nongnu.org; Wed, 03 Jan 2018 20:29:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eWuLV-0007EA-Ri for qemu-devel@nongnu.org; Wed, 03 Jan 2018 20:29:26 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:58657) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eWuLV-0007CO-HF for qemu-devel@nongnu.org; Wed, 03 Jan 2018 20:29:25 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue105 [212.227.15.183]) with ESMTPSA (Nemesis) id 0Lp6ay-1f9I1u1tFU-00eqQo; Thu, 04 Jan 2018 02:29:22 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 4 Jan 2018 02:29:10 +0100 Message-Id: <20180104012913.30763-15-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180104012913.30763-1-laurent@vivier.eu> References: <20180104012913.30763-1-laurent@vivier.eu> X-Provags-ID: V03:K0:MLVAix6Uc/CN6rlK8HK8/wgMjXR8G+QKqLRKVpjXswpli/a1VbG Iru3Ym4U2/XlAyG4Z5tiR3YHugLqLraajHnvksJ1U70R1rZpGi83KlB43NjmmA+Qpx5I1r5 PtYYhPQFeqgRA1rrgsuKMTQ+vcN39HFHmYY5heyxQqf4BFgxyur5T5DFMcPma+knNWgobJ/ 3yt+aGm67XhXLGJ16ZBZA== X-UI-Out-Filterresults: notjunk:1; V01:K0:Cil3UMzkAzw=:8UpKPO3rhdIWFg8KCr9M0x TbjxOQsduFrFmoEN2xEPPK8FDC3MF8RVYLIXQX2y40YXk25OO8mEpTXdNnoS+1E83KRgvtgz5 SGGn5OZZQ09tg+obxv0HoSHNsur9PmaKxNacJo6K6idqe6IpaaNPm4uciYwDettfhl1ErRp9T tZ31HqkhcsY+unbSkmucXDw8o0Vzgtm68LNhKoYDu48Abti4Gmfan9fJyt6MMCvJ3/rDc5B/y AI19mUFOaoBekWnFyVXVhTFmGPy4ygt11dRiKY0lm6MlK16xZKniDeW6cAozaGFxm5gyUDicz 7H+bhGwgalvZ4h9Wh9LeUAM83DHXcN2gFZjgAiCg1LABbgoPFoEyE880YzlwmIG14TrYNUXun 15XacXPICKCBqhIOeBIkiZTGt+cWYYW/FtJR4Wkk7HMA5HS3cjmNdSG0QvoMmWBWR1GrA1MHb 5j387YQ8od4gnkPZhdwcXhBAn3xqlGKjU8b0F1WeXtCsIT5XQhQdbUF53r42X3bSk/VntHcrg TFRMqwdGMeFxa3rllUk2OhtMuo23CVVxHpmKbpiZZxHwy6QmGU+pQ7b2NXja76zqI/prMmXuf Dzm6bbCmmU1YaN+Ouun2nWpba3LXUojGE82ABGr+LDWYcGZkKCB+BQL4YBIcoTr7HWPGUkVeF K6LVCe6K4jTL8UXg08DldJOB/q3J/jv/+HsolGPbazeCIzoZxrfUbM1+JF+d+FbpUbpXVpdu7 TnPWo1oiv779K81f6EfIH4TzC93mmqUhXhPYcPCP1ellvLFOYY+/CoaRMS7uPHX4iyoXtzCfp msjJWfKj8kBG8vMEpZhHcl11VfDFmFmsQSa1H/d+R0icy2cRKfVtHlxen8rLo8CRDYNpEgFBD PiAvXqCKWdhkK3nsJgxGSdKogyNzcK8xiRW/eYKJviGsrNX2THT+rE6B4MomVM X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.72.192.74 Subject: [Qemu-devel] [PATCH v7 14/17] target/m68k: add 680x0 "move to SR" instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Some cleanup, and allows SR to be moved from any addressing mode. Previous code was wrong for coldfire: coldfire also allows to use addressing mode to set SR/CCR. It only supports Data register to get SR/CCR (move from) Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target/m68k/translate.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 1f867a4f7a..8f23cade04 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2162,27 +2162,34 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); } else { - gen_helper_set_sr(cpu_env, tcg_const_i32(val)); + TCGv sr = tcg_const_i32(val); + gen_helper_set_sr(cpu_env, sr); + tcg_temp_free(sr); } set_cc_op(s, CC_OP_FLAGS); } -static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, - int ccr_only) +static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only) { - if ((insn & 0x38) == 0) { - if (ccr_only) { - gen_helper_set_ccr(cpu_env, DREG(insn, 0)); - } else { - gen_helper_set_sr(cpu_env, DREG(insn, 0)); - } - set_cc_op(s, CC_OP_FLAGS); - } else if ((insn & 0x3f) == 0x3c) { + if (ccr_only) { + gen_helper_set_ccr(cpu_env, val); + } else { + gen_helper_set_sr(cpu_env, val); + } + set_cc_op(s, CC_OP_FLAGS); +} + +static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, + bool ccr_only) +{ + if ((insn & 0x3f) == 0x3c) { uint16_t val; val = read_im16(env, s); gen_set_sr_im(s, val, ccr_only); } else { - disas_undef(env, s, insn); + TCGv src; + SRC_EA(env, src, OS_WORD, 0, NULL); + gen_set_sr(s, src, ccr_only); } } @@ -2557,7 +2564,7 @@ DISAS_INSN(neg) DISAS_INSN(move_to_ccr) { - gen_set_sr(env, s, insn, 1); + gen_move_to_sr(env, s, insn, true); } DISAS_INSN(not) @@ -4409,7 +4416,7 @@ DISAS_INSN(move_to_sr) gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); return; } - gen_set_sr(env, s, insn, 0); + gen_move_to_sr(env, s, insn, false); gen_lookup_tb(s); } @@ -5556,9 +5563,8 @@ void register_m68k_insns (CPUM68KState *env) BASE(move_to_ccr, 44c0, ffc0); INSN(not, 4680, fff8, CF_ISA_A); INSN(not, 4600, ff00, M68000); - INSN(undef, 46c0, ffc0, M68000); #if defined(CONFIG_SOFTMMU) - INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); + BASE(move_to_sr, 46c0, ffc0); #endif INSN(nbcd, 4800, ffc0, M68000); INSN(linkl, 4808, fff8, M68000);