From patchwork Sat Dec 9 08:43:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 846542 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yv2yn0wM5z9sCZ for ; Sat, 9 Dec 2017 19:52:01 +1100 (AEDT) Received: from localhost ([::1]:40454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eNarX-0007Po-5Y for incoming@patchwork.ozlabs.org; Sat, 09 Dec 2017 03:51:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eNakc-0001HY-UM for qemu-devel@nongnu.org; Sat, 09 Dec 2017 03:44:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eNakY-000786-Vm for qemu-devel@nongnu.org; Sat, 09 Dec 2017 03:44:50 -0500 Received: from 10.mo6.mail-out.ovh.net ([87.98.157.236]:34636) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eNakY-00077Q-Mq for qemu-devel@nongnu.org; Sat, 09 Dec 2017 03:44:46 -0500 Received: from player735.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 9A8AD1277C6 for ; Sat, 9 Dec 2017 09:44:45 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr [90.76.52.173]) (Authenticated sender: clg@kaod.org) by player735.ha.ovh.net (Postfix) with ESMTPSA id 6E99316009E; Sat, 9 Dec 2017 09:44:39 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson , Benjamin Herrenschmidt , Greg Kurz Date: Sat, 9 Dec 2017 09:43:27 +0100 Message-Id: <20171209084338.29395-9-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171209084338.29395-1-clg@kaod.org> References: <20171209084338.29395-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11708514606667172691 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtuddrvddugdduvdegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.157.236 Subject: [Qemu-devel] [PATCH v2 08/19] spapr: notify the CPU when the XIVE interrupt priority is more privileged X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Once an event has been routed, the XIVE virtualization presenter engine raises the bit corresponding to the priority of the pending interrupt in the register IBP (Interrupt Pending Buffer). The Pending Interrupt Priority Register (PIPR) is also updated using the IPB. It contains the priority of the most favored pending notification. The PIPR is then compared to the the Current Processor Priority Register (CPPR). If it is more favored (numerically less than), the CPU interrupt line is raised and the EO bit of the Notification Source Register (NSR) is updated to notify the presence of an exception for the O/S. The check needs to be done whenever the PIPR or the CPPR are changed. The O/S acknowledges the interrupt with a special load in the Thread Interrupt Management Area. If the EO bit of the NSR is set, the CPPR takes the value of PIPR. The bit number in the IBP corresponding to the priority of the pending interrupt is reseted and so is the EO bit of the NSR. Signed-off-by: Cédric Le Goater --- Changes since v1: - set initial TM_PIPR to 0xFF hw/intc/spapr_xive.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 629563d01998..a8acfee740d9 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -35,9 +35,68 @@ struct sPAPRXiveNVT { XiveEQ eqt[XIVE_PRIORITY_MAX + 1]; }; +/* Convert a priority number to an Interrupt Pending Buffer (IPB) + * register, which indicates a pending interrupt at the priority + * corresponding to the bit number + */ +static uint8_t priority_to_ipb(uint8_t priority) +{ + return priority > XIVE_PRIORITY_MAX ? + 0 : 1 << (XIVE_PRIORITY_MAX - priority); +} + +/* Convert an Interrupt Pending Buffer (IPB) register to a Pending + * Interrupt Priority Register (PIPR), which contains the priority of + * the most favored pending notification. + */ +static uint8_t ipb_to_pipr(uint8_t ibp) +{ + return ibp ? clz32((uint32_t)ibp << 24) : 0xff; +} + +/* + * TODO: + * + * Ben says: " + * + * PIPR is clamped to CPPR. So the value in the PIPR is: + * + * v = leftmost_bit_of(ipb) (or 0xff); + * pipr = v < cppr ? v : cppr; + * + * which means it's never actually 0xff ... surprise !". + * + * But, the CPPR is set to 0xFF by the OS and so the PIPR will always + * be more favored ... I am confused ... + */ static uint64_t spapr_xive_nvt_accept(sPAPRXiveNVT *nvt) { - return 0; + uint8_t nsr = nvt->ring_os[TM_NSR]; + + qemu_irq_lower(nvt->output); + + if (nvt->ring_os[TM_NSR] & TM_QW1_NSR_EO) { + uint8_t cppr = nvt->ring_os[TM_PIPR]; + + nvt->ring_os[TM_CPPR] = cppr; + + /* Reset the pending buffer bit */ + nvt->ring_os[TM_IPB] &= ~priority_to_ipb(cppr); + nvt->ring_os[TM_PIPR] = ipb_to_pipr(nvt->ring_os[TM_IPB]); + + /* Drop Exception bit for OS */ + nvt->ring_os[TM_NSR] &= ~TM_QW1_NSR_EO; + } + + return (nsr << 8) | nvt->ring_os[TM_CPPR]; +} + +static void spapr_xive_nvt_notify(sPAPRXiveNVT *nvt) +{ + if (nvt->ring_os[TM_PIPR] < nvt->ring_os[TM_CPPR]) { + nvt->ring_os[TM_NSR] |= TM_QW1_NSR_EO; + qemu_irq_raise(nvt->output); + } } static void spapr_xive_nvt_set_cppr(sPAPRXiveNVT *nvt, uint8_t cppr) @@ -47,6 +106,10 @@ static void spapr_xive_nvt_set_cppr(sPAPRXiveNVT *nvt, uint8_t cppr) } nvt->ring_os[TM_CPPR] = cppr; + + /* CPPR has changed, check if we need to redistribute a pending + * exception */ + spapr_xive_nvt_notify(nvt); } /* @@ -239,6 +302,8 @@ static void spapr_xive_irq(sPAPRXive *xive, int lisn) XiveEQ *eq; uint32_t eq_idx; uint8_t priority; + uint32_t server; + sPAPRXiveNVT *nvt; ive = spapr_xive_get_ive(xive, lisn); if (!ive || !(ive->w & IVE_VALID)) { @@ -267,6 +332,13 @@ static void spapr_xive_irq(sPAPRXive *xive, int lisn) qemu_log_mask(LOG_UNIMP, "XIVE: !UCOND_NOTIFY not implemented\n"); } + server = GETFIELD(EQ_W6_NVT_INDEX, eq->w6); + nvt = spapr_xive_nvt_get(xive, server); + if (!nvt) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVT for server %d\n", server); + return; + } + if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) { priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7); @@ -274,9 +346,18 @@ static void spapr_xive_irq(sPAPRXive *xive, int lisn) if (priority == 0xff) { g_assert_not_reached(); } + + /* Update the IPB (Interrupt Pending Buffer) with the priority + * of the new notification and inform the NVT, which will + * decide to raise the exception, or not, depending the CPPR. + */ + nvt->ring_os[TM_IPB] |= priority_to_ipb(priority); + nvt->ring_os[TM_PIPR] = ipb_to_pipr(nvt->ring_os[TM_IPB]); } else { qemu_log_mask(LOG_UNIMP, "XIVE: w7 format1 not implemented\n"); } + + spapr_xive_nvt_notify(nvt); } /* @@ -717,6 +798,12 @@ static void spapr_xive_nvt_reset(void *dev) memset(nvt->regs, 0, sizeof(nvt->regs)); + /* + * Initialize PIPR to 0xFF to avoid phantom interrupts when the + * CPPR is first set. + */ + nvt->ring_os[TM_PIPR] = ipb_to_pipr(nvt->ring_os[TM_IPB]); + memset(nvt->eqt, 0, sizeof(nvt->eqt)); }