From patchwork Mon Dec 4 03:48:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 844075 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="WekyV/FU"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yqrTH2D9Lz9s1h for ; Mon, 4 Dec 2017 14:48:51 +1100 (AEDT) Received: from localhost ([::1]:41077 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eLhkP-0005aF-EG for incoming@patchwork.ozlabs.org; Sun, 03 Dec 2017 22:48:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eLhjn-0005Z0-Nv for qemu-devel@nongnu.org; Sun, 03 Dec 2017 22:48:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eLhjl-0004Lb-TF for qemu-devel@nongnu.org; Sun, 03 Dec 2017 22:48:11 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:39841) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eLhjl-0004KE-AH; Sun, 03 Dec 2017 22:48:09 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3yqrSQ1rb0z9s7g; Mon, 4 Dec 2017 14:48:05 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1512359286; bh=zNgiOSO79BunZjDw5Y3ag0Mlh4OAk6hEBg6HmEQ49g4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WekyV/FUaN1yNgc/CfI8QbDFlXTezk/kVOA8+ZrD9wZtaKcrFhKCiLvHpPXYQjXtS XuEJxs8y0SGEVcxZgICwtJf91aWkzl4CRp6OaW+M0rHKyLOsJJ4LCEj/xyPMSX7y1L NKf/IgFsoxLFNxD40k0dgBB0/vDrU4xdm0ktivqA= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 4 Dec 2017 14:48:01 +1100 Message-Id: <20171204034802.7336-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171204034802.7336-1-david@gibson.dropbear.id.au> References: <20171204034802.7336-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 2/3] target-ppc: Don't invalidate non-supported msr bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kurban Mallachiev , qemu-devel@nongnu.org, agraf@suse.de, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Kurban Mallachiev The msr invalidation code (commits 993eb and 2360b) inverts all bits except MSR_TGPR and MSR_HVB. On non PowerPC 601 processors this leads to incorrect change of excp_prefix in hreg_store_msr() function. The problem is that new msr value get multiplied by msr_mask and inverted msr does not, thus values of MSR_EP bit in new msr value and inverted msr are distinct, so that excp_prefix changes but should not. Signed-off-by: Kurban Mallachiev Signed-off-by: David Gibson --- target/ppc/machine.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 24117e8f31..e475206c6a 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -300,9 +300,9 @@ static int cpu_post_load(void *opaque, int version_id) ppc_store_sdr1(env, env->spr[SPR_SDR1]); } - /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ + /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */ msr = env->msr; - env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); hreg_compute_mem_idx(env);