From patchwork Wed Oct 4 18:43:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 821446 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="hyFNsxdM"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y6lDm0fGBz9t69 for ; Thu, 5 Oct 2017 05:44:24 +1100 (AEDT) Received: from localhost ([::1]:36426 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzoec-0008Cb-3R for incoming@patchwork.ozlabs.org; Wed, 04 Oct 2017 14:44:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dzodq-00089k-LT for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dzodp-0002cD-Nf for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:34 -0400 Received: from mail-qt0-x233.google.com ([2607:f8b0:400d:c0d::233]:43756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dzodp-0002bg-JI for qemu-devel@nongnu.org; Wed, 04 Oct 2017 14:43:33 -0400 Received: by mail-qt0-x233.google.com with SMTP id a43so15130923qta.0 for ; Wed, 04 Oct 2017 11:43:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3scm5MUW7GUgyfh34S1Vo3Ln+aBGgTxbTJqlG1RMo0Y=; b=hyFNsxdM7mv8C6EQ6USs0ULOxFGlpM0Bfq5kObLwQIFSzFHItPTPIW//y7xbVHvfY0 ucY16HvBwtJ85Cc7ynGtlrork8dWciqtrb18XgisA/xUaijCgY5i9mNk/jUvvvtaeBVO SXE0ckYntDUbQmLrrwtO5o3gZfqus0bbgiHqg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3scm5MUW7GUgyfh34S1Vo3Ln+aBGgTxbTJqlG1RMo0Y=; b=VmQDdvj+7fHUeUKwNNPqpwH4+cXJyLlvXHl3IZYn+XqDz7X+1RcxX3O0c5IXjl6nUn TaNeNHIXvyv3U0zs8dW0ava4BH1gD93wHpiQBy1/MECub9KqrCsCRqM/fdSxJzCiEZax RRo2t5DrGB1m9vzBVQE4n8/NwkKbKeu25r7PyQCcwO3ScSQZdOMgKpsPbackl0L/IDtj Hl5ijtko4SI7ZUxpY/NofYn/aPr/JQVteHrCcgcub5aErPh1b51Z0BFFitcbB3ZvDdM1 BsNHAboRFNm/3FTK39B999wg2DeVO7nH0sMeSj6tuCezPhMu+msHq2NlBBr+s6Q5qQzK a69g== X-Gm-Message-State: AMCzsaVjul+/jrEidcJbBd+2d2roEdOp9GIBbCoE3/jz+2utnbvSnuDz +wfZPd3I8zJhIvy0objhMJtIKjSEVLY= X-Google-Smtp-Source: AOwi7QBOmZpQdNFyhwtv9boN0+r822rs9ZmA9MSjTfjzmQFlNyoGdHctkdEjchh9mcC6qdpS06yufQ== X-Received: by 10.37.194.130 with SMTP id s124mr4787132ybf.271.1507142612679; Wed, 04 Oct 2017 11:43:32 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2606:a000:7a4a:b100::1b]) by smtp.gmail.com with ESMTPSA id o64sm3020464ywe.12.2017.10.04.11.43.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Oct 2017 11:43:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Oct 2017 14:43:15 -0400 Message-Id: <20171004184325.24157-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org> References: <20171004184325.24157-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::233 Subject: [Qemu-devel] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/cpu.h | 1 + linux-user/elfload.c | 9 +++++++++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + 4 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 69cb49acc3..c5c9cef834 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1312,6 +1312,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 79062882ba..003d9420b7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,14 @@ enum { ARM_HWCAP_A64_SHA1 = 1 << 5, ARM_HWCAP_A64_SHA2 = 1 << 6, ARM_HWCAP_A64_CRC32 = 1 << 7, + ARM_HWCAP_A64_ATOMICS = 1 << 8, + ARM_HWCAP_A64_FPHP = 1 << 9, + ARM_HWCAP_A64_ASIMDHP = 1 << 10, + ARM_HWCAP_A64_CPUID = 1 << 11, + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, + ARM_HWCAP_A64_JSCVT = 1 << 13, + ARM_HWCAP_A64_FCMA = 1 << 14, + ARM_HWCAP_A64_LRCPC = 1 << 15, }; #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +540,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_1_SIMD, ARM_HWCAP_A64_ASIMDRDM); #undef GET_FEATURE return hwcaps; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4300de66e2..276c996e9f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1603,6 +1603,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); cpu->midr = 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6e..b05c904ad2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }