From patchwork Wed Aug 30 08:26:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Andres Gomez Del Real X-Patchwork-Id: 807471 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BweAw+o7"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xhzH732jhz9t0M for ; Wed, 30 Aug 2017 18:30:59 +1000 (AEST) Received: from localhost ([::1]:48994 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmyOn-0004iX-41 for incoming@patchwork.ozlabs.org; Wed, 30 Aug 2017 04:30:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60517) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmyLi-0002U9-IC for qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmyLd-0000MA-LM for qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:46 -0400 Received: from mail-ua0-x241.google.com ([2607:f8b0:400c:c08::241]:33570) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmyLd-0000M0-GU for qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:41 -0400 Received: by mail-ua0-x241.google.com with SMTP id m24so2359737uai.0 for ; Wed, 30 Aug 2017 01:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jzEcn9QaLxWhhgD1UNz6wDNI4BEyG/k48wc+rPl342g=; b=BweAw+o7JY9vgt4cUmeBiPYToBa0pEvfSYy3GpW4efDdjLKDsIinrpkgY2f/TB+bhK bJ7CUldH9j4eIoFDSOSTe5RC4BxMvnY2CbdD/Vimd26oujyyiVEewqwY6+wYY6iTzEsz k//xoz0XhTzM9DGRubEArhd/kCPy4jCBtqXFP3TJYtWgYLo+n5XdVPFa+VLWM2bEeBqj JL46TaWSG9KMj6nFUypvcvliK8eHC7A9XZhjnODbnt6vHKSuZ6khIEPA1nxtQ3eu1gTo EsVvAOFh1TY6COxXQcz2m7GOJirPEmAC2tIYHzi2pGJidqTDvrl0WrrVkHsE06f6IgpD gWZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jzEcn9QaLxWhhgD1UNz6wDNI4BEyG/k48wc+rPl342g=; b=dk+3JWnxW2emQsxQiSCXiY6561FFvxO5zthnJdyvRb7A7n1RKY6b7DRsqjJEhMu8tr nxJrHD1ou/H5Plhf+sP06EIFS9Pk8Ft/epnMh/ScGkZLak3F2xKdcF7EZAJFfrYkYz9k R4ONlfZYes9iVGsnL0Vgc8FyStdCqE24yvWdWPExSivbnvdLEpfm4L6BGWjCzyKWE5c2 /GHe/WTSKqDSe+e0hC+D8yakleU9PxgJ59YP8Zuj7w8Y7iGnwknbxV5yMUX24YhtM13u Eq73rY812AUTN2OxeVZ/DwC98zn7nYCxYw1H6LdPpUNMG2CeWj9R/Vw+p+GNTdVsiJha 61mQ== X-Gm-Message-State: AHPjjUg7E8qVs52xFwnhVuHKpHzfcns665LJtj3Uz8pWLUcZ9Hw4gYlt 3JEwS2FzeQ7qHcVl X-Received: by 10.159.49.78 with SMTP id n14mr453343uab.200.1504081660772; Wed, 30 Aug 2017 01:27:40 -0700 (PDT) Received: from localhost.localdomain ([191.109.6.85]) by smtp.gmail.com with ESMTPSA id h74sm1079197vka.8.2017.08.30.01.27.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 01:27:40 -0700 (PDT) From: Sergio Andres Gomez Del Real X-Google-Original-From: Sergio Andres Gomez Del Real To: qemu-devel@nongnu.org Date: Wed, 30 Aug 2017 03:26:54 -0500 Message-Id: <20170830082702.3011-6-Sergio.G.DelReal@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170830082702.3011-1-Sergio.G.DelReal@gmail.com> References: <20170830082702.3011-1-Sergio.G.DelReal@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400c:c08::241 Subject: [Qemu-devel] [PATCH v2 05/13] hvf: add fields to CPUState and CPUX86State; add definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sergio Andres Gomez Del Real Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This commit adds some fields specific to hvf in CPUState and CPUX86State. It also adds some handy #defines. Signed-off-by: Sergio Andres Gomez Del Real --- include/qom/cpu.h | 2 ++ target/i386/cpu.h | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 25eefea7ab..fb0e54e6d9 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -407,6 +407,8 @@ struct CPUState { * unnecessary flushes. */ uint16_t pending_tlb_flush; + + uint64_t hvf_fd; }; QTAILQ_HEAD(CPUTailQ, CPUState); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 051867399b..7d90f08b98 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -82,15 +82,19 @@ #define R_GS 5 /* segment descriptor fields */ +#define DESC_G_SHIFT 23 #define DESC_G_MASK (1 << 23) #define DESC_B_SHIFT 22 #define DESC_B_MASK (1 << DESC_B_SHIFT) #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ #define DESC_L_MASK (1 << DESC_L_SHIFT) +#define DESC_AVL_SHIFT 20 #define DESC_AVL_MASK (1 << 20) +#define DESC_P_SHIFT 15 #define DESC_P_MASK (1 << 15) #define DESC_DPL_SHIFT 13 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) +#define DESC_S_SHIFT 12 #define DESC_S_MASK (1 << 12) #define DESC_TYPE_SHIFT 8 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) @@ -631,6 +635,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ +#define CPUID_7_0_ECX_AVX512BMI (1U << 1) #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ #define CPUID_7_0_ECX_UMIP (1U << 2) #define CPUID_7_0_ECX_PKU (1U << 3) @@ -806,6 +811,20 @@ typedef struct SegmentCache { float64 _d_##n[(bits)/64]; \ } +typedef union { + uint8_t _b[16]; + uint16_t _w[8]; + uint32_t _l[4]; + uint64_t _q[2]; +} XMMReg; + +typedef union { + uint8_t _b[32]; + uint16_t _w[16]; + uint32_t _l[8]; + uint64_t _q[4]; +} YMMReg; + typedef MMREG_UNION(ZMMReg, 512) ZMMReg; typedef MMREG_UNION(MMXReg, 64) MMXReg; @@ -1041,7 +1060,11 @@ typedef struct CPUX86State { ZMMReg xmm_t0; MMXReg mmx_t0; + XMMReg ymmh_regs[CPU_NB_REGS]; + uint64_t opmask_regs[NB_OPMASK_REGS]; + YMMReg zmmh_regs[CPU_NB_REGS]; + ZMMReg hi16_zmm_regs[CPU_NB_REGS]; /* sysenter registers */ uint32_t sysenter_cs;