From patchwork Mon Jul 24 20:27:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 793063 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="czDfztDH"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xGY8G4tK2z9s2G for ; Tue, 25 Jul 2017 06:37:18 +1000 (AEST) Received: from localhost ([::1]:56859 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZk6O-0001Pk-GL for incoming@patchwork.ozlabs.org; Mon, 24 Jul 2017 16:37:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxh-00035a-7c for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxd-0000up-N1 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:17 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:36992) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxd-0000ud-Iy for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:13 -0400 Received: by mail-qk0-x244.google.com with SMTP id q130so10950556qka.4 for ; Mon, 24 Jul 2017 13:28:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8MTYGPv73oD6SmPYjv27jPVXkfKXlmN90Q8mDaYzCfY=; b=czDfztDHeoAwBy6otN/l63lvi+CvSPt3q/NigFl9KEY8bDqlcHAUJ8jTeGAW+r2K1o /tjOZ3wQxAGYytlyJPWClX5ENfjqkPchArJVOg534+X3g/m3z0Zd0Ig1zjfLTsdKnpLl 85jfr6JUNf38NcqZs3A2GPjx2dQH23Y2uMHoQrRbCPSqGh8rc2n+g3Luz+vqKff8lUmE wzxF87zDyMqq5tNaFns5bNEdZIePGu7utnnhZxYtMp+M1as0nyX1BdiA6Punh5Fn0YsP N/azbtQUn1E3RXsR/dY95diyRF4KVFeIjy5yONZCrC0XFmuF9GtpLDCp6zi5gTS3gH4I eo9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8MTYGPv73oD6SmPYjv27jPVXkfKXlmN90Q8mDaYzCfY=; b=Oi+v+UZwgm3Yk/2Be6mMUzqnQ3h9zuK6Fy0UQ66HRHVzc7/j6uR17lWl6XgUFY/QQn 6coWpjCO2iYSyU+of5joHOrDkNG6HKmc6CGLNBRMACCv8Ez/T0a+lxvCJzPn6KIfQzhN QGfaZ04XrDae9GKxWGHuU2+9rydsQ/pKZpdAUGn0EJj5NuvuHsVJzB211JvFt+6Q7Axe lN4q4fOSaCs4f1fkvFqqqVwaI1HAjx1BRWIRjI7ao9fbl4Xqqv73TcVXxiGK4OXlbQVM imvdA0mVG6le7KPzPuiKYHI89yQ+3Qm42BETPwg5JzUH7HIXEc/txACq7LsI853oYs6B PeWA== X-Gm-Message-State: AIVw1136zD90JBIBCsqMsoIiwSEEoZaYjb8KSmD/NYqyq40o7LfLtMFZ onv/T3rwfYokkqKw0gE= X-Received: by 10.233.237.211 with SMTP id c202mr21676453qkg.1.1500928092754; Mon, 24 Jul 2017 13:28:12 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:04 -0700 Message-Id: <20170724202728.25960-9-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 08/32] target/i386: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Signed-off-by: Lluís Vilanova Message-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 +++++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 7825593111..651abcaf38 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8376,20 +8376,13 @@ void tcg_x86_init(void) } } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu, + int max_insns) { - CPUX86State *env = cs->env_ptr; - DisasContext dc1, *dc = &dc1; - uint32_t flags; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.pc_first = tb->pc; - cs_base = tb->cs_base; - flags = tb->flags; + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUX86State *env = cpu->env_ptr; + uint32_t flags = dc->base.tb->flags; + target_ulong cs_base = dc->base.tb->cs_base; dc->pe = (flags >> HF_PE_SHIFT) & 1; dc->code32 = (flags >> HF_CS32_SHIFT) & 1; @@ -8400,11 +8393,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; - dc->base.singlestep_enabled = cs->singlestep_enabled; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->cs_base = cs_base; - dc->base.tb = tb; dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; @@ -8422,7 +8413,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags = flags; - dc->jmp_opt = !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8434,7 +8425,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) record/replay modes and there will always be an additional step for ecx=0 when icount is enabled. */ - dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt = !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8454,9 +8445,24 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) cpu_ptr1 = tcg_temp_new_ptr(); cpu_cc_srcT = tcg_temp_local_new(); + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUX86State *env = cs->env_ptr; + DisasContext dc1, *dc = &dc1; + int num_insns; + int max_insns; + + /* generate intermediate code */ + dc->base.singlestep_enabled = cs->singlestep_enabled; + dc->base.tb = tb; dc->base.is_jmp = DISAS_NEXT; + dc->base.pc_first = tb->pc; dc->base.pc_next = dc->base.pc_first; - num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; @@ -8464,7 +8470,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns = TCG_MAX_INSNS; } + max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns); + num_insns = 0; gen_tb_start(tb); for(;;) { tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); @@ -8497,7 +8505,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { + (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break;