From patchwork Fri Jun 23 16:22:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 780153 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wvPmC0VDWz9s1h for ; Sat, 24 Jun 2017 02:58:35 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Hk8jCQbm"; dkim-atps=neutral Received: from localhost ([::1]:36419 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dORui-0002U6-R2 for incoming@patchwork.ozlabs.org; Fri, 23 Jun 2017 12:58:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60407) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dORMS-0001mG-9k for qemu-devel@nongnu.org; Fri, 23 Jun 2017 12:23:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dORMQ-00080o-Uo for qemu-devel@nongnu.org; Fri, 23 Jun 2017 12:23:08 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:34642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dORMQ-00080Z-PC for qemu-devel@nongnu.org; Fri, 23 Jun 2017 12:23:06 -0400 Received: by mail-qt0-x242.google.com with SMTP id w6so5861208qtg.1 for ; Fri, 23 Jun 2017 09:23:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=pAx0JE7XjKOaK99PuldkpgvcB43xHBIBcKgCZsH9nHc=; b=Hk8jCQbmawxc/qGtUV5RlkxF0D1wRDtqsmbWIt1v7ejk6MGcMz+SuyYfTV85MY0WfS rkTyPTrwLKQcLY3/Q006YOgoCmyBq5LrlvHFsD+1stnn5miZDyPclKxGtIUxwtHSbPDt z+FgEG0Zd8pvH6yWkcNjABtTIPyQb+/KOq94wWUcgnmDYFWo/2xv7eHiKrBD0QWfYvGx KgdOM2fOfJXYD2/jKxI9D1GFf2Z2M1PSJkxPsG2HYIF1satxzeuOnOu8WunD5ZafzBIa 0SLNCSB1t7lNJ5ScLDfr9hEf7Slwo3DdMKpKz8LYIdPnM6YuTeRZHrOaetozIpqinY1B OfVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=pAx0JE7XjKOaK99PuldkpgvcB43xHBIBcKgCZsH9nHc=; b=VmrfI+reJRJaJaESaBq++9HcV++DDnRfgAnFLvSk1FUcMuBMVlkGE0bS8nCpTWec9W f2t0ZdTS0ywYap9Bb7ONirL5W0G+PHIyPV1n48OAb8TxMN749eGppC3ATEduvlW7k2ot eWYMzkC+QVGyH0qU+Ao+v/djWt3Yof7q1RimzLui6FyZ4iie0p6jBqwWxaKPgzbvtAoZ +T/YFW4zMyEwBrAlGpIWRy8vmgU3uvekJxmRCSOx/LL962EyvUCLxlXbi7ED/y+fX9qW SyxUPnkLpLPMT+Uox7SEc9cyPSeL4c7jqfaGNHz6Ol0UbCjyHqucBmuRCzR7RYC6tsJp akqg== X-Gm-Message-State: AKS2vOynS1YkR64jqKE+EZ14UcxI1lfvGjr3RwxGNpiD825LG2rnssMT dTA2TZ4227s49ndkgws= X-Received: by 10.200.34.55 with SMTP id o52mr10559691qto.67.1498234985959; Fri, 23 Jun 2017 09:23:05 -0700 (PDT) Received: from bigtime.twiddle.net.com (97-113-165-157.tukw.qwest.net. [97.113.165.157]) by smtp.gmail.com with ESMTPSA id p52sm3743567qtb.69.2017.06.23.09.23.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Jun 2017 09:23:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Jun 2017 09:22:41 -0700 Message-Id: <20170623162241.8964-16-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170623162241.8964-1-rth@twiddle.net> References: <20170623162241.8964-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: David Hildenbrand Let's keep it very simple for now and flush the complete tlb, we currently can't find the right entries in our tlb, we would have to store the used tables for each element. As we now fully implement the DAT-enhancement facility, we can allow to enable it for the qemu CPU model. Signed-off-by: David Hildenbrand Message-Id: <20170622094151.28633-4-david@redhat.com> Signed-off-by: Richard Henderson --- target/s390x/cpu_models.c | 1 + target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 ++ target/s390x/mem_helper.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++ target/s390x/translate.c | 15 ++++++++++++++ 5 files changed, 70 insertions(+) diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 51b17b9..63903c2 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -675,6 +675,7 @@ static void check_compatibility(const S390CPUModel *max_model, static void add_qemu_cpu_model_features(S390FeatBitmap fbm) { static const int feats[] = { + S390_FEAT_DAT_ENH, S390_FEAT_STFLE, S390_FEAT_EXTENDED_IMMEDIATE, S390_FEAT_EXTENDED_TRANSLATION_2, diff --git a/target/s390x/helper.h b/target/s390x/helper.h index b268367..964097b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_4(mvcs, i32, env, i64, i64, i64) DEF_HELPER_4(mvcp, i32, env, i64, i64, i64) DEF_HELPER_4(sigp, i32, env, i64, i32, i64) DEF_HELPER_FLAGS_2(sacf, TCG_CALL_NO_WG, void, env, i64) +DEF_HELPER_FLAGS_4(idte, TCG_CALL_NO_RWG, void, env, i64, i64, i32) DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32) DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 5ba7822..d3bb851 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -928,6 +928,8 @@ C(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0) /* INSERT STORAGE KEY EXTENDED */ C(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0) +/* INVALIDATE DAT TABLE ENTRY */ + C(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0) /* INVALIDATE PAGE TABLE ENTRY */ C(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0) /* LOAD CONTROL */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 20cef9a..ede8471 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1610,6 +1610,57 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2) return cc; } +void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4) +{ + CPUState *cs = CPU(s390_env_get_cpu(env)); + const uintptr_t ra = GETPC(); + uint64_t table, entry, raddr; + uint16_t entries, i, index = 0; + + if (r2 & 0xff000) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIFICATION, 4); + } + + if (!(r2 & 0x800)) { + /* invalidation-and-clearing operation */ + table = r1 & _ASCE_ORIGIN; + entries = (r2 & 0x7ff) + 1; + + switch (r1 & _ASCE_TYPE_MASK) { + case _ASCE_TYPE_REGION1: + index = (r2 >> 53) & 0x7ff; + break; + case _ASCE_TYPE_REGION2: + index = (r2 >> 42) & 0x7ff; + break; + case _ASCE_TYPE_REGION3: + index = (r2 >> 31) & 0x7ff; + break; + case _ASCE_TYPE_SEGMENT: + index = (r2 >> 20) & 0x7ff; + break; + } + for (i = 0; i < entries; i++) { + /* addresses are not wrapped in 24/31bit mode but table index is */ + raddr = table + ((index + i) & 0x7ff) * sizeof(entry); + entry = ldq_phys(cs->as, raddr); + if (!(entry & _REGION_ENTRY_INV)) { + /* we are allowed to not store if already invalid */ + entry |= _REGION_ENTRY_INV; + stq_phys(cs->as, raddr, entry); + } + } + } + + /* We simply flush the complete tlb, therefore we can ignore r3. */ + if (m4 & 1) { + tlb_flush(cs); + } else { + tlb_flush_all_cpus_synced(cs); + } +} + /* invalidate pte */ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, uint32_t m4) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 1db5f2d..592d6b0 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2380,6 +2380,21 @@ static ExitStatus op_ipm(DisasContext *s, DisasOps *o) } #ifndef CONFIG_USER_ONLY +static ExitStatus op_idte(DisasContext *s, DisasOps *o) +{ + TCGv_i32 m4; + + check_privileged(s); + if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { + m4 = tcg_const_i32(get_field(s->fields, m4)); + } else { + m4 = tcg_const_i32(0); + } + gen_helper_idte(cpu_env, o->in1, o->in2, m4); + tcg_temp_free_i32(m4); + return NO_EXIT; +} + static ExitStatus op_ipte(DisasContext *s, DisasOps *o) { TCGv_i32 m4;