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[qemu] spapr_pci: Warn when RAM page size is not enabled in IOMMU page mask

Message ID 20170328081349.18734-1-aik@ozlabs.ru
State New
Headers show

Commit Message

Alexey Kardashevskiy March 28, 2017, 8:13 a.m. UTC
If a page size used by QEMU is not enabled in the PHB IOMMU page mask,
in-kernel acceleration of TCE handling won't be enabled and performance
might be slower than expected.

This prints a warning if system page size is not enabled. This should
print a warning if huge pages are enabled but sphb.pgsz still uses
the default value of 4K|64K.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---

This follow-up for "exec, spapr_pci: Advertise huge IOMMU pages".
Instead of silently changing PHB properties+behaviour for better
performance if huge pages are detected, this simply warns the user
if IOMMU page mask needs to be adjusted. Since the user chooses
huge pages in the first place, the user can also supply additional
page masks as well.


---
 hw/ppc/spapr_pci.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

David Gibson March 29, 2017, 5:10 a.m. UTC | #1
On Tue, Mar 28, 2017 at 07:13:49PM +1100, Alexey Kardashevskiy wrote:
> If a page size used by QEMU is not enabled in the PHB IOMMU page mask,
> in-kernel acceleration of TCE handling won't be enabled and performance
> might be slower than expected.
> 
> This prints a warning if system page size is not enabled. This should
> print a warning if huge pages are enabled but sphb.pgsz still uses
> the default value of 4K|64K.
> 
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> 
> This follow-up for "exec, spapr_pci: Advertise huge IOMMU pages".
> Instead of silently changing PHB properties+behaviour for better
> performance if huge pages are detected, this simply warns the user
> if IOMMU page mask needs to be adjusted. Since the user chooses
> huge pages in the first place, the user can also supply additional
> page masks as well.

Applied to ppc-for-2.10.

> 
> 
> ---
>  hw/ppc/spapr_pci.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
> index 98c52e411f..097ebdd51d 100644
> --- a/hw/ppc/spapr_pci.c
> +++ b/hw/ppc/spapr_pci.c
> @@ -1771,6 +1771,12 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
>      }
>  
>      /* DMA setup */
> +    if ((sphb->page_size_mask & qemu_getrampagesize()) == 0) {
> +        error_report("System page size 0x%lx is not enabled in page_size_mask "
> +                     "(0x%"PRIx64"). Performance may be slow",
> +                     qemu_getrampagesize(), sphb->page_size_mask);
> +    }
> +
>      for (i = 0; i < windows_supported; ++i) {
>          tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
>          if (!tcet) {
diff mbox

Patch

diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 98c52e411f..097ebdd51d 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1771,6 +1771,12 @@  static void spapr_phb_realize(DeviceState *dev, Error **errp)
     }
 
     /* DMA setup */
+    if ((sphb->page_size_mask & qemu_getrampagesize()) == 0) {
+        error_report("System page size 0x%lx is not enabled in page_size_mask "
+                     "(0x%"PRIx64"). Performance may be slow",
+                     qemu_getrampagesize(), sphb->page_size_mask);
+    }
+
     for (i = 0; i < windows_supported; ++i) {
         tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
         if (!tcet) {