From patchwork Thu Feb 9 04:51:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 725953 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vJmNr6JPMz9s4s for ; Thu, 9 Feb 2017 16:10:20 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Jiuf0B02"; dkim-atps=neutral Received: from localhost ([::1]:35600 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgzq-0001al-Cn for incoming@patchwork.ozlabs.org; Thu, 09 Feb 2017 00:10:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38203) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgj2-0002UP-Jq for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbgj1-0007vQ-CF for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:56 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:35952) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbgj1-0007vK-54 for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:55 -0500 Received: by mail-pg0-x242.google.com with SMTP id 75so16791569pgf.3 for ; Wed, 08 Feb 2017 20:52:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=pFSMa4rgR1dBksYI7hWlWPt9vvZP7mKfjSPqvfLf0+I=; b=Jiuf0B02QhnmlCUcb2KAwVSwcNJ+/nx4SRj4TQKbbAIVrslYoGlWz5rMJtVHFxSbYH s+tmQatNibCbW6N/K64lEyq1K9QVAl8GFtQ6ti8dvLQaGDuwyulHvnAWmHrKPYDS/iql CfXr6hiNfmEsaPIP7Da2JecHOpN9zWpxBotT1rtvIeJlrACVt5kY2T/Wy2gUSAc4Ws36 mLqR9HsXjeDQXVipMBdEEibKIW6eDogSHMQjs9uxL3bVgSJmR7+m1iw+aAqkKIsLv7ys vjE0vVeJ/J2wXsDjdchsszob3ufPR8RoOdEy8wZSGgwae26LxG4dEJ61AvxE1Sr4TY9G MIdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=pFSMa4rgR1dBksYI7hWlWPt9vvZP7mKfjSPqvfLf0+I=; b=BuKig5JhAeMgSsFK6piUgJNMQw88iQptTw0IJq/2UVwr9LFcVaLwnxFUTKKvNc6lOw q/AjDs3iw5RNS3INOD4FNxjMfPAge5AOk2V1CvgirDN7JKFFVCdrY8e+lmSRz8HBM7HH jQIPayCAhtbAHujWftHKBLQdlODCNoFA9hk1/tob7mT5KlpaYVPaKC1Y3J96ahNXuW/6 ETlvKm6v06odbBNW1cOdIdMWRCYcDkiIxv16Y3xFjcEPC+sTOm24O3uAT7qc7WK+YYoe IDjpppR8PZ1q1PIUfmdhLmJnRhG0BeGuIgi1cUDxZ3FwKK750jbCLfnp02RRPpOcAfLm Hg6g== X-Gm-Message-State: AMke39mPvyH44FWToCyIMDIzueTmoOGJlVLh8RahR8X51kybefkpY5GvO+FU2Ow1bJXmTg== X-Received: by 10.99.238.69 with SMTP id n5mr1630047pgk.38.1486615974205; Wed, 08 Feb 2017 20:52:54 -0800 (PST) Received: from bigtime.home ([1.128.80.123]) by smtp.gmail.com with ESMTPSA id b75sm24202832pfb.90.2017.02.08.20.52.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Feb 2017 20:52:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Feb 2017 20:51:49 -0800 Message-Id: <20170209045154.16868-18-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170209045154.16868-1-rth@twiddle.net> References: <20170209045154.16868-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 17/22] target/openrisc: Represent MACHI:MACLO as a single unit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Significantly simplifies the implementation of the use of MAC. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 3 +- target/openrisc/machine.c | 5 +- target/openrisc/sys_helper.c | 13 +++++ target/openrisc/translate.c | 120 +++++++++++++++++++++++-------------------- 4 files changed, 80 insertions(+), 61 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82b87b3..1ee1210 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -277,8 +277,7 @@ typedef struct CPUOpenRISCState { target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ - target_ulong machi; /* Multiply register MACHI */ - target_ulong maclo; /* Multiply register MACLO */ + uint64_t mac; /* Multiply registers MACHI:MACLO */ target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */ target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */ diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index b723138..4100957 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -47,8 +47,8 @@ static const VMStateInfo vmstate_sr = { static const VMStateDescription vmstate_env = { .name = "env", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), @@ -82,6 +82,7 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(immucfgr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), + VMSTATE_UINT64(mac, CPUOpenRISCState), VMSTATE_END_OF_LIST() } }; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 4a59728..9841a5b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -120,6 +120,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ break; + case TO_SPR(5, 1): /* MACLO */ + env->mac = deposit64(env->mac, 0, 32, rb); + break; + case TO_SPR(5, 2): /* MACHI */ + env->mac = deposit64(env->mac, 32, 32, rb); + break; case TO_SPR(9, 0): /* PICMR */ env->picmr |= rb; break; @@ -245,6 +251,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ break; + case TO_SPR(5, 1): /* MACLO */ + return (uint32_t)env->mac; + break; + case TO_SPR(5, 2): /* MACHI */ + return env->mac >> 32; + break; + case TO_SPR(9, 0): /* PICMR */ return env->picmr; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index dd4ba8c..82b8bec 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -60,7 +60,7 @@ static TCGv cpu_sr_ov; /* signed overflow */ static TCGv cpu_lock_addr; static TCGv cpu_lock_value; static TCGv_i32 fpcsr; -static TCGv machi, maclo; +static TCGv_i64 cpu_mac; /* MACHI:MACLO */ static TCGv fpmaddhi, fpmaddlo; static TCGv_i32 env_flags; #include "exec/gen-icount.h" @@ -105,12 +105,9 @@ void openrisc_translate_init(void) fpcsr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUOpenRISCState, fpcsr), "fpcsr"); - machi = tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, machi), - "machi"); - maclo = tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, maclo), - "maclo"); + cpu_mac = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUOpenRISCState, mac), + "mac"); fpmaddhi = tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, fpmaddhi), "fpmaddhi"); @@ -365,6 +362,58 @@ static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) gen_ove_cy(dc); } +static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) +{ + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t1, srca); + tcg_gen_ext_tl_i64(t2, srcb); + tcg_gen_mul_i64(t1, t1, t2); + + /* Note that overflow is only computed during addition stage. */ + tcg_gen_xor_i64(t2, cpu_mac, t1); + tcg_gen_add_i64(cpu_mac, cpu_mac, t1); + tcg_gen_xor_i64(t1, t1, cpu_mac); + tcg_gen_andc_i64(t1, t1, t2); + tcg_temp_free_i64(t2); + +#if TARGET_LONG_BITS == 32 + tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); +#else + tcg_gen_mov_i64(cpu_sr_ov, t1); +#endif + tcg_temp_free_i64(t1); + + gen_ove_ov(dc); +} + +static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb) +{ + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t1, srca); + tcg_gen_ext_tl_i64(t2, srcb); + tcg_gen_mul_i64(t1, t1, t2); + + /* Note that overflow is only computed during subtraction stage. */ + tcg_gen_xor_i64(t2, cpu_mac, t1); + tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); + tcg_gen_xor_i64(t1, t1, cpu_mac); + tcg_gen_and_i64(t1, t1, t2); + tcg_temp_free_i64(t2); + +#if TARGET_LONG_BITS == 32 + tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); +#else + tcg_gen_mov_i64(cpu_sr_ov, t1); +#endif + tcg_temp_free_i64(t1); + + gen_ove_ov(dc); +} + static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) { TCGv ea = tcg_temp_new(); @@ -628,23 +677,9 @@ static void dec_misc(DisasContext *dc, uint32_t insn) case 0x13: /* l.maci */ LOG_DIS("l.maci r%d, %d\n", ra, I16); - { - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); - TCGv_i32 dst = tcg_temp_new_i32(); - TCGv ttmp = tcg_const_tl(I16); - tcg_gen_mul_tl(dst, cpu_R[ra], ttmp); - tcg_gen_ext_i32_i64(t1, dst); - tcg_gen_concat_i32_i64(t2, maclo, machi); - tcg_gen_add_i64(t2, t2, t1); - tcg_gen_extrl_i64_i32(maclo, t2); - tcg_gen_shri_i64(t2, t2, 32); - tcg_gen_extrl_i64_i32(machi, t2); - tcg_temp_free_i32(dst); - tcg_temp_free(ttmp); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - } + t0 = tcg_const_tl(I16); + gen_mac(dc, cpu_R[ra], t0); + tcg_temp_free(t0); break; case 0x09: /* l.rfe */ @@ -873,40 +908,12 @@ static void dec_mac(DisasContext *dc, uint32_t insn) switch (op0) { case 0x0001: /* l.mac */ LOG_DIS("l.mac r%d, r%d\n", ra, rb); - { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); - tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]); - tcg_gen_ext_i32_i64(t1, t0); - tcg_gen_concat_i32_i64(t2, maclo, machi); - tcg_gen_add_i64(t2, t2, t1); - tcg_gen_extrl_i64_i32(maclo, t2); - tcg_gen_shri_i64(t2, t2, 32); - tcg_gen_extrl_i64_i32(machi, t2); - tcg_temp_free_i32(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - } + gen_mac(dc, cpu_R[ra], cpu_R[rb]); break; case 0x0002: /* l.msb */ LOG_DIS("l.msb r%d, r%d\n", ra, rb); - { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); - tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]); - tcg_gen_ext_i32_i64(t1, t0); - tcg_gen_concat_i32_i64(t2, maclo, machi); - tcg_gen_sub_i64(t2, t2, t1); - tcg_gen_extrl_i64_i32(maclo, t2); - tcg_gen_shri_i64(t2, t2, 32); - tcg_gen_extrl_i64_i32(machi, t2); - tcg_temp_free_i32(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - } + gen_msb(dc, cpu_R[ra], cpu_R[rb]); break; default: @@ -969,9 +976,8 @@ static void dec_M(DisasContext *dc, uint32_t insn) case 0x1: /* l.macrc */ LOG_DIS("l.macrc r%d\n", rd); - tcg_gen_mov_tl(cpu_R[rd], maclo); - tcg_gen_movi_tl(maclo, 0x0); - tcg_gen_movi_tl(machi, 0x0); + tcg_gen_trunc_i64_tl(cpu_R[rd], cpu_mac); + tcg_gen_movi_i64(cpu_mac, 0); break; default: