From patchwork Thu Feb 2 05:14:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 722821 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vDVdb2FCxz9s7C for ; Thu, 2 Feb 2017 17:36:35 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="L9GQS1Cy"; dkim-atps=neutral Received: from localhost ([::1]:54674 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZB0S-0003NQ-QE for incoming@patchwork.ozlabs.org; Thu, 02 Feb 2017 01:36:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZ9k8-0007mq-Pa for qemu-devel@nongnu.org; Thu, 02 Feb 2017 00:15:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZ9k2-000482-OF for qemu-devel@nongnu.org; Thu, 02 Feb 2017 00:15:36 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:55537) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cZ9k2-00045H-7z; Thu, 02 Feb 2017 00:15:30 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vDSqW2hlkz9sD9; Thu, 2 Feb 2017 16:15:00 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1486012503; bh=cJw+h3qT1nhLrIVi9Vtj+rWABZb3GJdy0CCJ4uNaD5g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L9GQS1Cyop2L+xW64XYdW9sOcJpCPjPDJ8mO3AyKAGz3rBjWD9dSLDtC2rmT4s5yG +JKDvrS0ezqHN09PpRAkH0TI6lBFqK2xqO0hL2Nh7idI1z872rTPZYSS1WMvN85Rl2 zs0MSQNxI95D4zAGl7xah5rQtSIWHQhBs+GlU4qA= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 2 Feb 2017 16:14:10 +1100 Message-Id: <20170202051445.5735-73-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170202051445.5735-1-david@gibson.dropbear.id.au> References: <20170202051445.5735-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 072/107] ppc: Implement bcds. instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, Jose Ricardo Ziviani , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Jose Ricardo Ziviani bcds.: Decimal shift. Given two registers vra and vrb, this instruction shift the vrb value by vra bits into the result register. Signed-off-by: Jose Ricardo Ziviani Signed-off-by: David Gibson --- target/ppc/helper.h | 1 + target/ppc/int_helper.c | 40 +++++++++++++++++++++++++++++++++++++ target/ppc/translate/vmx-impl.inc.c | 3 +++ target/ppc/translate/vmx-ops.inc.c | 3 ++- 4 files changed, 46 insertions(+), 1 deletion(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ec0ae8a..26edbf9 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -393,6 +393,7 @@ DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32) DEF_HELPER_3(bcdctsq, i32, avr, avr, i32) DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32) DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32) +DEF_HELPER_4(bcds, i32, avr, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xsaddqp, void, env, i32) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 8cf4ee3..5f53710 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -3062,6 +3062,46 @@ uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) return bcd_cmp_zero(r); } +uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) +{ + int cr; +#if defined(HOST_WORDS_BIGENDIAN) + int i = a->s8[7]; +#else + int i = a->s8[8]; +#endif + bool ox_flag = false; + int sgnb = bcd_get_sgn(b); + ppc_avr_t ret = *b; + ret.u64[LO_IDX] &= ~0xf; + + if (bcd_is_valid(b) == false) { + return CRF_SO; + } + + if (unlikely(i > 31)) { + i = 31; + } else if (unlikely(i < -31)) { + i = -31; + } + + if (i > 0) { + ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag); + } else { + urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4); + } + bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0); + + *r = ret; + + cr = bcd_cmp_zero(r); + if (ox_flag) { + cr |= CRF_SO; + } + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index e8e527f..84ebb7e 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -1016,6 +1016,7 @@ GEN_BCD2(bcdcfsq) GEN_BCD2(bcdctsq) GEN_BCD2(bcdsetsgn) GEN_BCD(bcdcpsgn); +GEN_BCD(bcds); static void gen_xpnd04_1(DisasContext *ctx) { @@ -1090,6 +1091,8 @@ GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ bcdsub, PPC_NONE, PPC2_ALTIVEC_207) GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \ bcdcpsgn, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ + bcds, PPC_NONE, PPC2_ISA300) static void gen_vsbox(DisasContext *ctx) { diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c index 57dce6e..7b4b009 100644 --- a/target/ppc/translate/vmx-ops.inc.c +++ b/target/ppc/translate/vmx-ops.inc.c @@ -62,7 +62,8 @@ GEN_VXFORM_207(vaddudm, 0, 3), GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vsubuwm, 0, 18), -GEN_VXFORM_207(vsubudm, 0, 19), +GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), +GEN_VXFORM_300(bcds, 0, 27), GEN_VXFORM(vmaxub, 1, 0), GEN_VXFORM(vmaxuh, 1, 1), GEN_VXFORM(vmaxuw, 1, 2),