From patchwork Fri Jan 27 10:39:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 720633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v8xH23Flvz9s3s for ; Fri, 27 Jan 2017 22:23:10 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="QQXQQh2q"; dkim-atps=neutral Received: from localhost ([::1]:44482 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX4cV-0003Il-Tc for incoming@patchwork.ozlabs.org; Fri, 27 Jan 2017 06:23:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX3wY-0003Yd-2G for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:39:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cX3wV-0003cN-7u for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:39:46 -0500 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:35486) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cX3wV-0003bg-2H for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:39:43 -0500 Received: by mail-wm0-x22d.google.com with SMTP id r126so110951725wmr.0 for ; Fri, 27 Jan 2017 02:39:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y7zYZvE7n9D0dBB1IqY7SsdefFQddJx3kVYUDcVdxF0=; b=QQXQQh2qSOspvmGiLUM6MiTIS02IOOUKiFugU+qsL7gcXzK0e3o87rFSzZGa/i3lmb EGfRhfRP3GRkMf1XrpxejFt5z4CayROdYkxsHjURAmQ663Ivd44h/6m1sHsRACnuNWfr S//+SkGPIL9uRp4ROK10+v91/CPQq5eD/R2yI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y7zYZvE7n9D0dBB1IqY7SsdefFQddJx3kVYUDcVdxF0=; b=cklSKTUBlMYq9FizRA08/0VZTLvi795pIcaQ/rLiozKC1WjZwhcbtxnhi+rR6SBF57 1Vm49RI8vSnCYZqjdQDRNC9H34DAfxIQGW2s1DCawH17qJkjw+hWHIEsETRTJIWwmwL4 XFMoSgMGROwezacLgdBvzBpplJ5V5k9iyEbLvayd0TlE7KShOdgX2n0KTAteO98F0THm q0cKWgAdUE4irxBJ4c1IM2aJ0RKljaUUZ87PZMYE9ACSnF7EK87ZvJWK2vxhMrmpR94X pvWlFwsjD6GPRqmNzYLJBUE30JdL9jqquKZp9EcqQM8ikTnk3PxvQTrUWKmoEXKwHteS xt8w== X-Gm-Message-State: AIkVDXJZbIYAbHRFTMYkqns630QFHuoq/T9nmQmZaz48OtUFmIfKi5m7KU6JqPzrANrTItLl X-Received: by 10.28.8.213 with SMTP id 204mr2554194wmi.100.1485513582037; Fri, 27 Jan 2017 02:39:42 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id m29sm7156779wrm.38.2017.01.27.02.39.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 02:39:37 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 338623E3779; Fri, 27 Jan 2017 10:39:24 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Fri, 27 Jan 2017 10:39:19 +0000 Message-Id: <20170127103922.19658-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170127103922.19658-1-alex.bennee@linaro.org> References: <20170127103922.19658-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PATCH v8 22/25] target-arm/cpu.h: make ARM_CP defined consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, claudio.fontana@huawei.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, "open list:ARM" , serge.fdrv@gmail.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is a purely mechanical change to make the ARM_CP flags neatly align and use a consistent format so it is easier to see which bit each flag is. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 274ef17562..f56a96c675 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1398,20 +1398,20 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. */ -#define ARM_CP_SPECIAL 1 -#define ARM_CP_CONST 2 -#define ARM_CP_64BIT 4 -#define ARM_CP_SUPPRESS_TB_END 8 -#define ARM_CP_OVERRIDE 16 -#define ARM_CP_ALIAS 32 -#define ARM_CP_IO 64 -#define ARM_CP_NO_RAW 128 -#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) -#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_SPECIAL (1 << 0) +#define ARM_CP_CONST (1 << 1) +#define ARM_CP_64BIT (1 << 2) +#define ARM_CP_SUPPRESS_TB_END (1 << 3) +#define ARM_CP_OVERRIDE (1 << 4) +#define ARM_CP_ALIAS (1 << 5) +#define ARM_CP_IO (1 << 6) +#define ARM_CP_NO_RAW (1 << 7) +#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) +#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) +#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */