From patchwork Thu Jan 19 17:05:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 717269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v49kW1MnDz9syB for ; Fri, 20 Jan 2017 04:26:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="jSLG0x/1"; dkim-atps=neutral Received: from localhost ([::1]:49918 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUGUC-0001sQ-Lz for incoming@patchwork.ozlabs.org; Thu, 19 Jan 2017 12:26:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38958) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUG9X-0007jf-8T for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cUG9W-0007w6-5f for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:35 -0500 Received: from mail-wm0-x229.google.com ([2a00:1450:400c:c09::229]:35701) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cUG9V-0007vw-VR for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:34 -0500 Received: by mail-wm0-x229.google.com with SMTP id r126so2402570wmr.0 for ; Thu, 19 Jan 2017 09:05:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rnhlO3YtVU7sByD1dcfVTM+ieZtwBvWrK8Zd/XdlYEQ=; b=jSLG0x/1XNiSX1cnSEEqqPxfaBcZ+n6Bk5fPt0npYNsAKeEJ4S8LHQHPTtySNTjIr6 k1lMnPLQH1Gv1WZct6WJpmh/7MAJ7x669n9L3+XR26hY/jx/LxbpgA5/01wdKyvrlg/z Lgo2IkD+Vpguxv8Y1khxypi21UrQA9ztEJXqc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rnhlO3YtVU7sByD1dcfVTM+ieZtwBvWrK8Zd/XdlYEQ=; b=VSIAaqlE4gSnPuKHL6TnxUZPqGNQAJ2Iwom05rL9Ep4VURIpeb6ISKr3FDoKgGp1/K 0r8+gtToaPomRC/M4IPG8z/t/Bx6qPrghDLO1ZUMkfAY3PF8BuYgg2vCxYYzVv3fobwL TR8Qsu5+U57lK1sOBt6S1toHuMEAZb1aStbzHSt1jJgxQ4tobCMTuDdDH5fzb78uTQDq iMZiZ8V8KhTL6lyeAOeDjWKJrElKsRzJ5WKLwAeF0wOxcqXGCfleut9jGVddnThXNo0p /JqkAe33JpCEjjRZ78cZReS95GmlQxMWCn3KH1bIc6jUp26LpQGqBBtWoTWnoSHIdijG 9/Sw== X-Gm-Message-State: AIkVDXIRpst+9WgHre8fh0NBAf8QnUnXPFP5rHPVlfoJZQyX0HDIfnfPdhG2kFilMTaabTjG X-Received: by 10.223.169.114 with SMTP id u105mr8386650wrc.173.1484845532959; Thu, 19 Jan 2017 09:05:32 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id l9sm54520826wmf.18.2017.01.19.09.05.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jan 2017 09:05:24 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id A82F73E2A48; Thu, 19 Jan 2017 17:05:09 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Thu, 19 Jan 2017 17:05:06 +0000 Message-Id: <20170119170507.16185-27-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170119170507.16185-1-alex.bennee@linaro.org> References: <20170119170507.16185-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::229 Subject: [Qemu-devel] [PATCH v7 26/27] tcg: enable MTTCG by default for ARM on x86 hosts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, claudio.fontana@huawei.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, "open list:ARM" , serge.fdrv@gmail.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This enables the multi-threaded system emulation by default for ARMv7 and ARMv8 guests using the x86_64 TCG backend. This is because on the guest side: - The ARM translate.c/translate-64.c have been converted to - use MTTCG safe atomic primitives - emit the appropriate barrier ops - The ARM machine has been updated to - hold the BQL when modifying shared cross-vCPU state - defer cpu_reset to async safe work All the host backends support the barrier and atomic primitives but need to provide same-or-better support for normal load/store operations. Signed-off-by: Alex Bennée --- v7 - drop configure check for backend - declare backend memory order for x86 - declare guest memory order for ARM - add configure snippet to set TARGET_SUPPORTS_MTTCG --- configure | 6 ++++++ target/arm/cpu.h | 3 +++ tcg/i386/tcg-target.h | 16 ++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/configure b/configure index 17d52cdd74..a23245fdf4 100755 --- a/configure +++ b/configure @@ -5881,6 +5881,7 @@ mkdir -p $target_dir echo "# Automatically generated by configure - do not modify" > $config_target_mak bflt="no" +mttcg="no" interp_prefix1=$(echo "$interp_prefix" | sed "s/%M/$target_name/g") gdb_xml_files="" @@ -5899,11 +5900,13 @@ case "$target_name" in arm|armeb) TARGET_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; aarch64) TARGET_BASE_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; cris) @@ -6055,6 +6058,9 @@ if test "$target_bigendian" = "yes" ; then fi if test "$target_softmmu" = "yes" ; then echo "CONFIG_SOFTMMU=y" >> $config_target_mak + if test "$mttcg" = "yes" ; then + echo "TARGET_SUPPORTS_MTTCG=y" >> $config_target_mak + fi fi if test "$target_user_only" = "yes" ; then echo "CONFIG_USER_ONLY=y" >> $config_target_mak diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 29d15fc522..659e246a54 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,6 +29,9 @@ # define TARGET_LONG_BITS 32 #endif +/* ARM processors have a weak memory model */ +#define TCG_DEFAULT_MO (0) + #define CPUArchState struct CPUARMState #include "qemu-common.h" diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 21d96ec35c..536190f647 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -165,4 +165,20 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +/* This defines the natural memory order supported by this + * architecture before guarantees made by various barrier + * instructions. + * + * The x86 has a pretty strong memory ordering which only really + * allows for some stores to be re-ordered after loads. + */ +#include "tcg-mo.h" + +static inline int get_tcg_target_mo(void) +{ + return TCG_MO_ALL & ~TCG_MO_LD_ST; +} + +#define TCG_TARGET_DEFAULT_MO get_tcg_target_mo() + #endif