From patchwork Fri Dec 9 11:48:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 704421 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tZrJp6kMqz9vFV for ; Fri, 9 Dec 2016 22:55:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Ox2/lml8"; dkim-atps=neutral Received: from localhost ([::1]:46059 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cFJlo-0004zo-UG for incoming@patchwork.ozlabs.org; Fri, 09 Dec 2016 06:55:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41742) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cFJgL-0007Bb-Fe for qemu-devel@nongnu.org; Fri, 09 Dec 2016 06:49:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cFJgK-0007oO-8H for qemu-devel@nongnu.org; Fri, 09 Dec 2016 06:49:41 -0500 Received: from mail-wj0-f176.google.com ([209.85.210.176]:36486) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cFJgJ-0007o3-Vi for qemu-devel@nongnu.org; Fri, 09 Dec 2016 06:49:40 -0500 Received: by mail-wj0-f176.google.com with SMTP id tk12so12536160wjb.3 for ; Fri, 09 Dec 2016 03:49:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7NhxYOrUFwt5xILxi40lDt6CgK2jGg2SKdpl8xt0trQ=; b=Ox2/lml8uVBpCyYQwcxmjzhxbbP0M+kD6JRMcfojH0MlOmPy8lCwR6zFJT5nnI/9Ko TuHEpdvWlb8g/f6YIYj2r0dZ6rZL41UWiUBDVwNPUCG8kRvxwJnrgjp6nQiJfWbdf6+D BAEAWWIQljTsFCGJwLm2H0SEZ7z93DVo4CYRc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7NhxYOrUFwt5xILxi40lDt6CgK2jGg2SKdpl8xt0trQ=; b=UV1mgJquwD1EH3VhYQnSZft+mc390vZ+1cd3DSdf3c4MtjniDlO//AHCS0B9+rj0Qi zVK1/Utb8OOpMJXXaP17pPHS1ogZ6WHb09igTM0jtgezt7RUxTwJv0g7xuVnl2VvJ0kb LBOyF3Be88mgGPta5NRD9ALzOi8JYoUpANK6WN5OhuCrHtp4LG8ulZZ6OqnYU+ITvYV9 Bak0kOz51PZ2bHg9SvkxwjJr1uo8BoqpEaeTbzTSwX8LWuNqV0GcmB5lkDpCn7PdJLRY JVL2c5fitJwXTURTjd+Akulgx9sVyecDoiBBnIbByX21p1aplKY6Ono7MeepmQ3AZAXF 7GMw== X-Gm-Message-State: AKaTC02uIDXOhyon3FNhFJJDOzECgdlTtVxC6fsmzJCQ4hHT48ACwKbTpyvXUhuTord8fD8g X-Received: by 10.194.176.10 with SMTP id ce10mr40467546wjc.155.1481284118856; Fri, 09 Dec 2016 03:48:38 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id j1sm41944249wjm.26.2016.12.09.03.48.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Dec 2016 03:48:37 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 9E15F3E06E6; Fri, 9 Dec 2016 11:48:34 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 9 Dec 2016 11:48:22 +0000 Message-Id: <20161209114830.9158-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20161209114830.9158-1-alex.bennee@linaro.org> References: <20161209114830.9158-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.176 Subject: [Qemu-devel] [RISU PATCH v3 02/10] aarch64: add hand-coded risu skeleton for directed testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , joserz@linux.vnet.ibm.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Sometimes you want absolute control over your test set-up to feed explicit values into the test. This started as an experiment but might be useful for further developing tests. Signed-off-by: Alex Bennée --- Makefile | 7 ++ aarch64_simd_handcoded.risu.S | 208 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 215 insertions(+) create mode 100644 aarch64_simd_handcoded.risu.S diff --git a/Makefile b/Makefile index bfa8cac..4202c35 100644 --- a/Makefile +++ b/Makefile @@ -36,6 +36,13 @@ $(PROG): $(OBJS) %.risu.asm: %.risu.bin ${OBJDUMP} -b binary -m $(ARCH) -D $^ > $@ +# hand-coded tests +%.risu.bin: %.risu.elf + $(OBJCOPY) -O binary $< $@ + +%.risu.elf: %.risu.S + ${AS} -o $@ $^ + %.o: %.c $(HDRS) $(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $< diff --git a/aarch64_simd_handcoded.risu.S b/aarch64_simd_handcoded.risu.S new file mode 100644 index 0000000..61bd11a --- /dev/null +++ b/aarch64_simd_handcoded.risu.S @@ -0,0 +1,208 @@ +/* + Hand coded RISU tests for aarch64 + + Sometimes you want slightly more than random instructions and you + want a specifically crafted test but within RISU's framework. + + This file offers such a thing. + # So the last nibble indicates the desired operation: +my $OP_COMPARE = 0; # compare registers +my $OP_TESTEND = 1; # end of test, stop +my $OP_SETMEMBLOCK = 2; # r0 is address of memory block (8192 bytes) +my $OP_GETMEMBLOCK = 3; # add the address of memory block to r0 +my $OP_COMPAREMEM = 4; # compare memory block + + */ + +.macro risuop_comp + .word 0x00005af0 +.endm +.macro risuop_testend + .word 0x00005af1 +.endm + + .org 0x0 + +//.globl .data + mov x0, #0x0 // #0 + msr fpsr, x0 + mov x0, #0x0 // #0 + msr fpcr, x0 + mrs x0, nzcv + eor w0, w0, #0xf0000000 + msr nzcv, x0 + adr x0, _q0 + eor x0, x0, #0xf + b reg_setup + + /* + + This is the of block of data used for ld/st and setting up vector regs + Each .word is 32bits of data + + */ + .align 16 + +_q0: .word 0x70000000, 0xffffffff, 0x80000000, 0xffffffff +_q1: .word 0x90000000, 0x00000000, 0xa0000000, 0x00000000 +_q2: .word 0xffff0000, 0x00000000, 0xeeee0000, 0x00000000 +_q3: .word 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff +_q4: .word 0x80000000, 0x00000000, 0xf0000000, 0x00000000 +_q5: .word 0xffff0000, 0x00000000, 0xeeee0000, 0x00000000 +_q6: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q7: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +_q8: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q9: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q10: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q11: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q12: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q13: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q14: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q15: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +_q16: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q17: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q18: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q19: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q20: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q21: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q22: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q23: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +_q24: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q25: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q26: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q27: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q28: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q29: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q30: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q31: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + + .align 16 + + /* Setup the register state */ +reg_setup: + ldp q0, q1, [x0],#32 + ldp q2, q3, [x0],#16 + ldp q4, q5, [x0],#16 + ldp q6, q7, [x0],#16 + ldp q8, q9, [x0],#16 + ldp q10, q11, [x0],#16 + ldp q12, q13, [x0],#16 + ldp q14, q15, [x0],#16 + ldp q16, q17, [x0],#16 + ldp q18, q19, [x0],#16 + ldp q20, q21, [x0],#16 + ldp q22, q23, [x0],#16 + ldp q24, q25, [x0],#16 + ldp q26, q27, [x0],#16 + ldp q28, q29, [x0],#16 + ldp q30, q31, [x0],#16 + + /* Set-up integer registers */ + mov x0, #0 + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 + + risuop_comp + + /* Testing ursra */ + + ursra v16.2d, v0.2d, #64 + risuop_comp + ursra v17.2d, v1.2d, #64 + risuop_comp + ursra v18.2d, v2.2d, #64 + risuop_comp + ursra v19.2d, v3.2d, #64 + risuop_comp + ursra v20.2d, v4.2d, #64 + risuop_comp + ursra v21.2d, v5.2d, #64 + risuop_comp + ursra v22.2d, v6.2d, #64 + risuop_comp + ursra v23.2d, v7.2d, #64 + risuop_comp + ursra v24.2d, v8.2d, #64 + risuop_comp + ursra v25.2d, v9.2d, #64 + risuop_comp + ursra v26.2d, v10.2d, #64 + risuop_comp + ursra v27.2d, v11.2d, #64 + risuop_comp + ursra v28.2d, v12.2d, #64 + risuop_comp + ursra v29.2d, v13.2d, #64 + risuop_comp + ursra v30.2d, v14.2d, #64 + risuop_comp + ursra v31.2d, v15.2d, #64 + risuop_comp + + /* second pass */ + ursra v16.2d, v0.2d, #64 + risuop_comp + ursra v17.2d, v1.2d, #64 + risuop_comp + ursra v18.2d, v2.2d, #64 + risuop_comp + ursra v19.2d, v3.2d, #64 + risuop_comp + ursra v20.2d, v4.2d, #64 + risuop_comp + ursra v21.2d, v5.2d, #64 + risuop_comp + ursra v22.2d, v6.2d, #64 + risuop_comp + ursra v23.2d, v7.2d, #64 + risuop_comp + ursra v24.2d, v8.2d, #64 + risuop_comp + ursra v25.2d, v9.2d, #64 + risuop_comp + ursra v26.2d, v10.2d, #64 + risuop_comp + ursra v27.2d, v11.2d, #64 + risuop_comp + ursra v28.2d, v12.2d, #64 + risuop_comp + ursra v29.2d, v13.2d, #64 + risuop_comp + ursra v30.2d, v14.2d, #64 + risuop_comp + ursra v31.2d, v15.2d, #64 + risuop_comp + + risuop_testend /* test end */