From patchwork Thu Oct 27 15:10:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 687761 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t4WT72d5Zz9vG0 for ; Fri, 28 Oct 2016 02:46:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=RPgf6wFX; dkim-atps=neutral Received: from localhost ([::1]:42406 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzmsi-0000bC-7r for incoming@patchwork.ozlabs.org; Thu, 27 Oct 2016 11:46:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45432) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzmTK-0003h7-Q5 for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:20:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzmTH-0004Oy-1A for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:20:02 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:34841) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bzmTG-0004Og-R0 for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:19:58 -0400 Received: by mail-wm0-x230.google.com with SMTP id e69so41513462wmg.0 for ; Thu, 27 Oct 2016 08:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+9pSE/g4PdnBfkzcoXOJScsAoqS6cnymzGrvO7rMBno=; b=RPgf6wFX5I0VKEpNF0Ei1cLsCMfyPrrJst7Wpj+7OLt0SBBUnEvMkH3+EsZKQaULvA OBir97Pau0uUBg/pZMzSiodFjfOiYwqR4XgVsQ0ywtGkKK0MsBD4rWgVD3wf2klQ/Glk Np1PPtXSqtvurrqddVQdb0i47DzlKuHjpBcfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+9pSE/g4PdnBfkzcoXOJScsAoqS6cnymzGrvO7rMBno=; b=CEOY6nODrKtt/TmFDlkRw2IQU2xD3JsTfpmE7ngy0CWhPi9N9pYkxUGrRw7ISN2iIv MkoRRIZUtCxWnXpjGbLVcY6vS2bRq7htut7hijCkK3QhEAy3gLcAdyetmWAtgWYRTeKo IKuiIebRO4Drkv87az9NrdG1D36Ou3NKS2k7XRCZDeSFvrzhqsZdn4j8dMwKa6djTmNx cTZ4PVMTAMJ4v8A1B5J1jg1ka6gf8y22kQvdk/hR7y3PKNkXXJxM/hRY5Hd351sqszi9 kw0hpiQtAuiZTCi/D1cUVXnvWQbJg8thoRMqk7sgwf1kLDkoGqYMBu5kcJK8xumAyqXu p6MA== X-Gm-Message-State: ABUngvegXdsUXZaIrbbHuj0KzgFI9F9v8rU1ZBemiDiGEffxqzCjysQBSAQlt15lsC6SttiW X-Received: by 10.194.83.166 with SMTP id r6mr7323052wjy.186.1477581597667; Thu, 27 Oct 2016 08:19:57 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id p3sm9010136wjr.31.2016.10.27.08.19.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Oct 2016 08:19:55 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 05D403E0458; Thu, 27 Oct 2016 16:11:01 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: pbonzini@redhat.com Date: Thu, 27 Oct 2016 16:10:21 +0100 Message-Id: <20161027151030.20863-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161027151030.20863-1-alex.bennee@linaro.org> References: <20161027151030.20863-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PATCH v5 24/33] cputlb: add assert_cpu_is_self checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, nikunj@linux.vnet.ibm.com, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, serge.fdrv@gmail.com, bobby.prani@gmail.com, rth@twiddle.net, =?UTF-8?q?Alex=20Benn=C3=A9e?= , fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For SoftMMU the TLB flushes are an example of a task that can be triggered on one vCPU by another. To deal with this properly we need to use safe work to ensure these changes are done safely. The new assert can be enabled while debugging to catch these cases. Signed-off-by: Alex Bennée --- cputlb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/cputlb.c b/cputlb.c index 986efaa..eec1c39 100644 --- a/cputlb.c +++ b/cputlb.c @@ -59,6 +59,12 @@ } \ } while (0) +#define assert_cpu_is_self(this_cpu) do { \ + if (DEBUG_TLB_GATE) { \ + g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + } \ + } while (0) + /* statistics */ int tlb_flush_count; @@ -78,6 +84,7 @@ void tlb_flush(CPUState *cpu, int flush_global) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("(%d)\n", flush_global); memset(env->tlb_table, -1, sizeof(env->tlb_table)); @@ -94,6 +101,7 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("start\n"); for (;;) { @@ -138,6 +146,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) int i; int mmu_idx; + assert_cpu_is_self(cpu); tlb_debug("page :" TARGET_FMT_lx "\n", addr); /* Check if we need to flush due to large pages. */ @@ -175,6 +184,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) va_start(argp, addr); + assert_cpu_is_self(cpu); tlb_debug("addr "TARGET_FMT_lx"\n", addr); /* Check if we need to flush due to large pages. */ @@ -263,6 +273,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; + assert_cpu_is_self(cpu); + env = cpu->env_ptr; for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -294,6 +306,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) int i; int mmu_idx; + assert_cpu_is_self(cpu); + vaddr &= TARGET_PAGE_MASK; i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -353,6 +367,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE; int asidx = cpu_asidx_from_attrs(cpu, attrs); + assert_cpu_is_self(cpu); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { tlb_add_large_page(env, vaddr, size);