From patchwork Mon Jul 18 22:43:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 649800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rtdlm69KTz9ryT for ; Tue, 19 Jul 2016 08:54:28 +1000 (AEST) Received: from localhost ([::1]:50704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHQf-0003tY-Ls for incoming@patchwork.ozlabs.org; Mon, 18 Jul 2016 18:54:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHGQ-0005N2-LC for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:43:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bPHGO-0005Ti-RI for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:43:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55088) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHGO-0005Tc-LK for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:43:48 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3BB9885547; Mon, 18 Jul 2016 22:43:48 +0000 (UTC) Received: from redhat.com (vpn1-7-82.ams2.redhat.com [10.36.7.82]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id u6IMhiDI020732; Mon, 18 Jul 2016 18:43:45 -0400 Date: Tue, 19 Jul 2016 01:43:43 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20160719014343-mutt-send-email-mst@redhat.com> References: <1468881010-27229-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1468881010-27229-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 18 Jul 2016 22:43:48 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 12/55] x86-iommu: introduce "intremap" property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Eduardo Habkost , Peter Xu , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Peter Xu Adding one property for intel-iommu devices to specify whether we should support interrupt remapping. By default, IR is disabled. To enable it, we should use (take Intel IOMMU as example): -device intel_iommu,intremap=on This property can be shared by Intel and future AMD IOMMUs. Signed-off-by: Peter Xu Signed-off-by: Peter Xu --- include/hw/i386/x86-iommu.h | 1 + hw/i386/x86-iommu.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h index b2401a6..699dd06 100644 --- a/include/hw/i386/x86-iommu.h +++ b/include/hw/i386/x86-iommu.h @@ -43,6 +43,7 @@ struct X86IOMMUClass { struct X86IOMMUState { SysBusDevice busdev; + bool intr_supported; /* Whether vIOMMU supports IR */ }; /** diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index f395139..4280839 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -59,9 +59,32 @@ static void x86_iommu_class_init(ObjectClass *klass, void *data) dc->realize = x86_iommu_realize; } +static bool x86_iommu_intremap_prop_get(Object *o, Error **errp) +{ + X86IOMMUState *s = X86_IOMMU_DEVICE(o); + return s->intr_supported; +} + +static void x86_iommu_intremap_prop_set(Object *o, bool value, Error **errp) +{ + X86IOMMUState *s = X86_IOMMU_DEVICE(o); + s->intr_supported = value; +} + +static void x86_iommu_instance_init(Object *o) +{ + X86IOMMUState *s = X86_IOMMU_DEVICE(o); + + /* By default, do not support IR */ + s->intr_supported = false; + object_property_add_bool(o, "intremap", x86_iommu_intremap_prop_get, + x86_iommu_intremap_prop_set, NULL); +} + static const TypeInfo x86_iommu_info = { .name = TYPE_X86_IOMMU_DEVICE, .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = x86_iommu_instance_init, .instance_size = sizeof(X86IOMMUState), .class_init = x86_iommu_class_init, .class_size = sizeof(X86IOMMUClass),