| Message ID | 20160531183928.29406-12-bobby.prani@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 31/05/16 21:39, Pranith Kumar wrote: > Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > target-arm/translate.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index c946c0e..e1b16c0 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7980,9 +7980,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) > gen_clrex(s); > return; > case 4: /* dsb */ > + ARCH(7); ARMv7 ARM says: "A DSB behaves as a DMB with the same arguments, and also has the additional properties...". Kind regards, Sergey > + return; > case 5: /* dmb */ > ARCH(7); > - /* We don't emulate caches so these are a no-op. */ > + tcg_gen_mb(TCG_MB_FULL); > return; > case 6: /* isb */ > /* We need to break the TB after this insn to execute > @@ -10330,8 +10332,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw > gen_clrex(s); > break; > case 4: /* dsb */ > + break; > case 5: /* dmb */ > - /* These execute as NOPs. */ > + tcg_gen_mb(TCG_MB_FULL); > break; > case 6: /* isb */ > /* We need to break the TB after this insn
On Thu, Jun 2, 2016 at 3:37 PM, Sergey Fedorov <serge.fdrv@gmail.com> wrote: > On 31/05/16 21:39, Pranith Kumar wrote: >> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> >> Signed-off-by: Richard Henderson <rth@twiddle.net> >> --- >> target-arm/translate.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/target-arm/translate.c b/target-arm/translate.c >> index c946c0e..e1b16c0 100644 >> --- a/target-arm/translate.c >> +++ b/target-arm/translate.c >> @@ -7980,9 +7980,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) >> gen_clrex(s); >> return; >> case 4: /* dsb */ >> + ARCH(7); > > ARMv7 ARM says: "A DSB behaves as a DMB with the same arguments, and > also has the additional properties...". > OK. I was just focusing on dmb for now. I will add translation for all other barriers too in the next version. Thanks!
diff --git a/target-arm/translate.c b/target-arm/translate.c index c946c0e..e1b16c0 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7980,9 +7980,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_clrex(s); return; case 4: /* dsb */ + ARCH(7); + return; case 5: /* dmb */ ARCH(7); - /* We don't emulate caches so these are a no-op. */ + tcg_gen_mb(TCG_MB_FULL); return; case 6: /* isb */ /* We need to break the TB after this insn to execute @@ -10330,8 +10332,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw gen_clrex(s); break; case 4: /* dsb */ + break; case 5: /* dmb */ - /* These execute as NOPs. */ + tcg_gen_mb(TCG_MB_FULL); break; case 6: /* isb */ /* We need to break the TB after this insn