| Message ID | 20150702144406.40bce749@kryten |
|---|---|
| State | New |
| Headers | show |
On 02.07.15 06:44, Anton Blanchard wrote: > We are setting SRR0 to the instruction before the one causing the > unaligned exception. A quick testcase: > > . = 0x100 > .globl _start > _start: > /* Cause a 0x600 */ > li 3,0x1 > stwcx. 3,0,3 > 1: b 1b > > . = 0x600 > 1: b 1b > > Built into something we can load as a BIOS image: > > gcc -mbig -c test.S > ld -EB -Ttext 0x0 -o test test.o > objcopy -O binary test test.bin > > Run with: > > qemu-system-ppc64 -nographic -bios test.bin > > Shows an incorrect SRR0 (points at the li): > > SRR0 0000000000000100 > > With the patch we get the correct SRR0: > > SRR0 0000000000000104 > > Signed-off-by: Anton Blanchard <anton@samba.org> Thanks, applied to ppc-next. Alex
On Thu, 2015-07-02 at 14:44 +1000, Anton Blanchard wrote: > We are setting SRR0 to the instruction before the one causing the > unaligned exception. A quick testcase: > ../.. > p_helper.c b/target-ppc/excp_helper.c > index b803475..4250106 100644 > --- a/target-ppc/excp_helper.c > +++ b/target-ppc/excp_helper.c > @@ -200,7 +200,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, > int excp_model, int excp) > /* Get rS/rD and rA from faulting opcode */ > env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4)) > & 0x03FF0000) >> 16;. You need to also fix the above to use env->nip instead of env->nip - 4 when generating DSISR > - goto store_current; > + goto store_next; > case POWERPC_EXCP_PROGRAM: /* Program exception > */ > switch (env->error_code & ~0xF) { > case POWERPC_EXCP_FP:
diff --git a/linux-user/main.c b/linux-user/main.c index c855bcc..9100130 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1650,7 +1650,7 @@ void cpu_loop(CPUPPCState *env) info.si_signo = TARGET_SIGBUS; info.si_errno = 0; info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->nip - 4; + info._sifields._sigfault._addr = env->nip; queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_PROGRAM: /* Program exception */ diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index b803475..4250106 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -200,7 +200,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Get rS/rD and rA from faulting opcode */ env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4)) & 0x03FF0000) >> 16; - goto store_current; + goto store_next; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { case POWERPC_EXCP_FP:
We are setting SRR0 to the instruction before the one causing the unaligned exception. A quick testcase: . = 0x100 .globl _start _start: /* Cause a 0x600 */ li 3,0x1 stwcx. 3,0,3 1: b 1b . = 0x600 1: b 1b Built into something we can load as a BIOS image: gcc -mbig -c test.S ld -EB -Ttext 0x0 -o test test.o objcopy -O binary test test.bin Run with: qemu-system-ppc64 -nographic -bios test.bin Shows an incorrect SRR0 (points at the li): SRR0 0000000000000100 With the patch we get the correct SRR0: SRR0 0000000000000104 Signed-off-by: Anton Blanchard <anton@samba.org> --- linux-user/main.c | 2 +- target-ppc/excp_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)