From patchwork Fri Jan 31 16:10:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 315759 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2BD3F2C00AD for ; Sat, 1 Feb 2014 03:51:16 +1100 (EST) Received: from localhost ([::1]:56776 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9GpZ-00057D-DT for incoming@patchwork.ozlabs.org; Fri, 31 Jan 2014 11:20:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9Ggt-0001pc-3X for qemu-devel@nongnu.org; Fri, 31 Jan 2014 11:11:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W9Gfl-0001ay-T6 for qemu-devel@nongnu.org; Fri, 31 Jan 2014 11:10:36 -0500 Received: from roura.ac.upc.edu ([147.83.33.10]:58494 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9Gfe-0001Q5-TR; Fri, 31 Jan 2014 11:10:23 -0500 Received: from gw.ac.upc.edu (gw.ac.upc.es [147.83.30.3]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id s0VGA3Nx006419; Fri, 31 Jan 2014 17:10:03 +0100 Received: from localhost (unknown [84.88.51.85]) by gw.ac.upc.edu (Postfix) with ESMTP id B42726B01C1; Fri, 31 Jan 2014 17:05:47 +0100 (CET) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Fri, 31 Jan 2014 17:10:03 +0100 Message-Id: <20140131161003.32741.52570.stgit@fimbulvetr.bsc.es> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <20140131160902.32741.2680.stgit@fimbulvetr.bsc.es> References: <20140131160902.32741.2680.stgit@fimbulvetr.bsc.es> User-Agent: StGit/0.16 MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id s0VGA3Nx006419 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.83.33.10 Cc: Peter Maydell , Jia Liu , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , Stefan Hajnoczi , "Edgar E. Iglesias" , Guan Xuetao , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 11/12] trace: [tcg] Include TCG-tracing header on all targets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Lluís Vilanova --- target-alpha/translate.c | 3 +++ target-arm/translate.c | 3 +++ target-cris/translate.c | 3 +++ target-i386/translate.c | 3 +++ target-lm32/translate.c | 3 +++ target-m68k/translate.c | 3 +++ target-microblaze/translate.c | 3 +++ target-mips/translate.c | 3 +++ target-openrisc/translate.c | 3 +++ target-ppc/translate.c | 3 +++ target-s390x/translate.c | 2 ++ target-sh4/translate.c | 3 +++ target-sparc/translate.c | 3 +++ target-unicore32/translate.c | 3 +++ target-xtensa/translate.c | 3 +++ 15 files changed, 44 insertions(+) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 1155e86..a0d5a31 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -26,6 +26,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #undef ALPHA_DEBUG_DISAS #define CONFIG_SOFTFLOAT_INLINE diff --git a/target-arm/translate.c b/target-arm/translate.c index 8d240e1..c8c0097 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -34,6 +34,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T) #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ diff --git a/target-cris/translate.c b/target-cris/translate.c index f990d59..1223de5 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -33,6 +33,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define DISAS_CRIS 0 #if DISAS_CRIS # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) diff --git a/target-i386/translate.c b/target-i386/translate.c index b0f2279..2b8a3e6 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -32,6 +32,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 6ea0ecd..f703c09 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -27,6 +27,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define DISAS_LM32 1 #if DISAS_LM32 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f54b94a..f30fd21 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -27,6 +27,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + //#define DEBUG_DISPATCH 1 /* Fake floating point. */ diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 270138c..275e87b 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -27,6 +27,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define SIM_COMPAT 0 #define DISAS_GNU 1 #define DISAS_MB 1 diff --git a/target-mips/translate.c b/target-mips/translate.c index ef0a2c3..abb5fe5 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -29,6 +29,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define MIPS_DEBUG_DISAS 0 //#define MIPS_DEBUG_SIGN_EXTENSIONS diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index b381477..d2c730c 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -31,6 +31,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define OPENRISC_DISAS #ifdef OPENRISC_DISAS diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c5c1108..783034b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -27,6 +27,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define CPU_SINGLE_STEP 0x1 #define CPU_BRANCH_STEP 0x2 #define GDBSTUB_SINGLE_STEP 0x4 diff --git a/target-s390x/translate.c b/target-s390x/translate.c index bc99a37..1c73029 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -42,6 +42,8 @@ static TCGv_ptr cpu_env; #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + /* Information that (most) every instruction needs to manipulate. */ typedef struct DisasContext DisasContext; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 661fc6c..9577203 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -28,6 +28,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + typedef struct DisasContext { struct TranslationBlock *tb; target_ulong pc; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6150b22..705b53a 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -32,6 +32,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + #define DEBUG_DISAS #define DYNAMIC_PC 1 /* dynamic pc value */ diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 4572890..e0d3275 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -23,6 +23,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + /* internal defines */ typedef struct DisasContext { target_ulong pc; diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 2d2df33..d04b975 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -41,6 +41,9 @@ #define GEN_HELPER 1 #include "helper.h" +#include "trace-tcg.h" + + typedef struct DisasContext { const XtensaConfig *config; TranslationBlock *tb;