From patchwork Sun Apr 1 07:28:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin O'Connor X-Patchwork-Id: 149906 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B8AC0B6FA8 for ; Sun, 1 Apr 2012 17:28:55 +1000 (EST) Received: from localhost ([::1]:55560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SEFDY-0002r7-G9 for incoming@patchwork.ozlabs.org; Sun, 01 Apr 2012 03:28:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SEFDO-0002qy-BM for qemu-devel@nongnu.org; Sun, 01 Apr 2012 03:28:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SEFDL-0004Pv-JJ for qemu-devel@nongnu.org; Sun, 01 Apr 2012 03:28:41 -0400 Received: from mail-qa0-f52.google.com ([209.85.216.52]:34000) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SEFDL-0004Pe-DX for qemu-devel@nongnu.org; Sun, 01 Apr 2012 03:28:39 -0400 Received: by qabg40 with SMTP id g40so1147989qab.4 for ; Sun, 01 Apr 2012 00:28:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=4+/FbCbfTfUsm6pui1BIxGT5NqqHtLG/W/c1DE/np+U=; b=WlLzg7NwuK1EVm9RvuMwM/z+tmgNw+dqRD+f8RNBmVDUUz9Nar5VGPd0i9Z5xHTSzo A9nxstszxhdSC7ObWXttyzeGR3y3+9RsobQPI3q3vUquAG8tAMpKd8ufUlFcvAfSmtC4 Jyn40VYUFUkTK3IPBMSYW3rIlKprjSrJxfe9B+3CefhJLPWiEquY1DAbcclfLD675DfO LcY2Rmz4Sn4CCjb9wA1ZpPUe6vMGtdlI1mY2fuFAB5ecoWCl9MajL+Oxng8wPN3EO1an 8jtWeG7pc/rA7+qVu88wYZ8wG6oyxwQIxOip355sQATG3yIVg5S0TtcuFHYRhAmVcOxQ BczQ== Received: by 10.224.181.197 with SMTP id bz5mr5780311qab.64.1333265316639; Sun, 01 Apr 2012 00:28:36 -0700 (PDT) Received: from localhost (207-172-165-101.c3-0.avec-ubr1.nyr-avec.ny.cable.rcn.com. [207.172.165.101]) by mx.google.com with ESMTPS id j17sm28059689qaj.9.2012.04.01.00.28.34 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 01 Apr 2012 00:28:35 -0700 (PDT) Date: Sun, 1 Apr 2012 03:28:34 -0400 From: Kevin O'Connor To: Alexey Korolev Message-ID: <20120401072834.GC17053@morn.localdomain> References: <1332908730.10322.4.camel@nzhmlwks0057.ad.endace.com> <1332910450.10322.26.camel@nzhmlwks0057.ad.endace.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1332910450.10322.26.camel@nzhmlwks0057.ad.endace.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQkcIBhWtNOWCaLUSmpW8Z9LPF3job2sr7sK+j9jMWRYY6387k4kiZwde/7I4GVRzxZu2KrZ X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.216.52 Cc: sfd@endace.com, seabios@seabios.org, qemu-devel@nongnu.org Subject: Re: [Qemu-devel] [PATCH 3/4] Switch from array based resource allocation to list X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Wed, Mar 28, 2012 at 05:54:10PM +1300, Alexey Korolev wrote: > In this patch instead of array based resource allocation approach > we calculate resource addresses linked lists of pci_region_entry structures. Thanks. I still think this migration can be done more seamlessly. I played with your patches a bit and came up with the attached patches that do just code movement - no alogorithm changes. See the attached. Also, I think we should look to commit after the next SeaBIOS release. -Kevin From 2f6e81d884dfbb01a12ddfb10a64bf87e864a19c Mon Sep 17 00:00:00 2001 From: Alexey Korolev Date: Wed, 28 Mar 2012 17:41:41 +1300 Subject: [PATCH 1/3] Added a pci_region_entry structure To: seabios@seabios.org In this patch the pci_region_entry structure is introduced. The pci_device->bars are removed. The information from pci_region_entry is used to program pci bars. Signed-off-by: Alexey Korolev Signed-off-by: Kevin O'Connor --- src/pci.h | 5 -- src/pciinit.c | 115 +++++++++++++++++++++++++++++++++++++++------------------ 2 files changed, 79 insertions(+), 41 deletions(-) diff --git a/src/pci.h b/src/pci.h index a2a5a4c..5598100 100644 --- a/src/pci.h +++ b/src/pci.h @@ -51,11 +51,6 @@ struct pci_device { u8 prog_if, revision; u8 header_type; u8 secondary_bus; - struct { - u32 addr; - u32 size; - int is64; - } bars[PCI_NUM_REGIONS]; // Local information on device. int have_driver; diff --git a/src/pciinit.c b/src/pciinit.c index 9f3fdd4..2831895 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -31,6 +31,19 @@ static const char *region_type_name[] = { [ PCI_REGION_TYPE_PREFMEM ] = "prefmem", }; +struct pci_bus; +struct pci_region_entry { + struct pci_device *dev; + int bar; + u32 size; + int is64; + enum pci_region_type type; + struct pci_bus *child_bus; + struct pci_bus *parent_bus; + struct pci_region_entry *next; + struct pci_region_entry **pprev; +}; + struct pci_bus { struct { /* pci region stats */ @@ -41,6 +54,7 @@ struct pci_bus { /* pci region assignments */ u32 bases[32 - PCI_MEM_INDEX_SHIFT]; u32 base; + struct pci_region_entry *list; } r[PCI_REGION_TYPE_COUNT]; struct pci_device *bus_dev; }; @@ -352,19 +366,33 @@ pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size) *size = (~(*val & mask)) + 1; } -static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size) +static struct pci_region_entry * +pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev, + u32 size, int type, int is64) { - u32 index; - - index = pci_size_to_index(size, type); + struct pci_region_entry *entry = malloc_tmp(sizeof(*entry)); + if (!entry) { + warn_noalloc(); + return NULL; + } + memset(entry, 0, sizeof(*entry)); + entry->dev = dev; + entry->size = size; + entry->is64 = is64; + entry->type = type; + entry->parent_bus = bus; + list_add_head(&bus->r[type].list, entry); + + u32 index = pci_size_to_index(size, type); size = pci_index_to_size(index, type); bus->r[type].count[index]++; bus->r[type].sum += size; if (bus->r[type].max < size) bus->r[type].max = size; + return entry; } -static void pci_bios_check_devices(struct pci_bus *busses) +static int pci_bios_check_devices(struct pci_bus *busses) { dprintf(1, "PCI: check devices\n"); @@ -383,14 +411,16 @@ static void pci_bios_check_devices(struct pci_bus *busses) if (val == 0) continue; - pci_bios_bus_reserve(bus, pci_addr_to_type(val), size); - pci->bars[i].addr = val; - pci->bars[i].size = size; - pci->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) && - (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) - == PCI_BASE_ADDRESS_MEM_TYPE_64); + int is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) && + (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) + == PCI_BASE_ADDRESS_MEM_TYPE_64); + struct pci_region_entry *entry = pci_region_create_entry( + bus, pci, size, pci_addr_to_type(val), is64); + if (!entry) + return -1; + entry->bar = i; - if (pci->bars[i].is64) + if (is64) i++; } } @@ -410,7 +440,11 @@ static void pci_bios_check_devices(struct pci_bus *busses) if (s->r[type].size < limit) s->r[type].size = limit; s->r[type].size = pci_size_roundup(s->r[type].size); - pci_bios_bus_reserve(parent, type, s->r[type].size); + struct pci_region_entry *entry = pci_region_create_entry( + parent, s->bus_dev, s->r[type].size, type, 0); + if (!entry) + return -1; + entry->child_bus = s; } dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n", secondary_bus, @@ -418,6 +452,7 @@ static void pci_bios_check_devices(struct pci_bus *busses) s->r[PCI_REGION_TYPE_MEM].size, s->r[PCI_REGION_TYPE_PREFMEM].size); } + return 0; } #define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1) @@ -483,6 +518,25 @@ static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size) #define PCI_MEMORY_SHIFT 16 #define PCI_PREF_MEMORY_SHIFT 16 +static void pci_region_map_one_entry(struct pci_region_entry *entry) +{ + if (!entry->child_bus) { + u32 addr = pci_bios_bus_get_addr( + entry->parent_bus, entry->type, entry->size); + dprintf(1, "PCI: map device bdf=%02x:%02x.%x" + " bar %d, addr %08x, size %08x [%s]\n", + pci_bdf_to_bus(entry->dev->bdf), + pci_bdf_to_dev(entry->dev->bdf), + pci_bdf_to_fn(entry->dev->bdf), + entry->bar, addr, entry->size, + region_type_name[entry->type]); + + pci_set_io_region_addr(entry->dev, entry->bar, addr); + if (entry->is64) + pci_set_io_region_addr(entry->dev, entry->bar + 1, 0); + } +} + static void pci_bios_map_devices(struct pci_bus *busses) { // Setup bases for root bus. @@ -526,28 +580,15 @@ static void pci_bios_map_devices(struct pci_bus *busses) } // Map regions on each device. - struct pci_device *pci; - foreachpci(pci) { - if (pci->class == PCI_CLASS_BRIDGE_PCI) - continue; - u16 bdf = pci->bdf; - dprintf(1, "PCI: map device bdf=%02x:%02x.%x\n" - , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)); - struct pci_bus *bus = &busses[pci_bdf_to_bus(bdf)]; - int i; - for (i = 0; i < PCI_NUM_REGIONS; i++) { - if (pci->bars[i].addr == 0) - continue; - - int type = pci_addr_to_type(pci->bars[i].addr); - u32 addr = pci_bios_bus_get_addr(bus, type, pci->bars[i].size); - dprintf(1, " bar %d, addr %x, size %x [%s]\n", - i, addr, pci->bars[i].size, region_type_name[type]); - pci_set_io_region_addr(pci, i, addr); - - if (pci->bars[i].is64) { - i++; - pci_set_io_region_addr(pci, i, 0); + int bus; + for (bus = 0; bus<=MaxPCIBus; bus++) { + int type; + for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { + struct pci_region_entry *entry, *next; + list_foreach_entry_safe(busses[bus].r[type].list, next, entry) { + pci_region_map_one_entry(entry); + list_del(entry); + free(entry); } } } @@ -588,7 +629,9 @@ pci_setup(void) return; } memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1)); - pci_bios_check_devices(busses); + if (pci_bios_check_devices(busses)) + return; + if (pci_bios_init_root_regions(&busses[0], start, end) != 0) { panic("PCI: out of address space\n"); }