From patchwork Wed Mar 14 12:41:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Starikovskiy X-Patchwork-Id: 146636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6FA0BB6EEF for ; Thu, 15 Mar 2012 02:06:26 +1100 (EST) Received: from localhost ([::1]:51370 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7oQT-000159-Cq for incoming@patchwork.ozlabs.org; Wed, 14 Mar 2012 09:39:37 -0400 Received: from eggs.gnu.org ([208.118.235.92]:54257) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7nVt-0006p9-QS for qemu-devel@nongnu.org; Wed, 14 Mar 2012 08:41:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7nVo-0003XV-Gi for qemu-devel@nongnu.org; Wed, 14 Mar 2012 08:41:09 -0400 Received: from nm6.bullet.mail.ird.yahoo.com ([77.238.189.63]:35612) by eggs.gnu.org with smtp (Exim 4.71) (envelope-from ) id 1S7nVn-0003XF-VH for qemu-devel@nongnu.org; Wed, 14 Mar 2012 08:41:04 -0400 Received: from [77.238.189.57] by nm6.bullet.mail.ird.yahoo.com with NNFMP; 14 Mar 2012 12:41:01 -0000 Received: from [217.146.188.239] by tm10.bullet.mail.ird.yahoo.com with NNFMP; 14 Mar 2012 12:41:01 -0000 Received: from [127.0.0.1] by smtp107.mail.ird.yahoo.com with NNFMP; 14 Mar 2012 12:41:01 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ymail.com; s=s1024; t=1331728861; bh=d29QDAFfdm+Gw/5EZHXrQMAooGH7KKL1HFwcEQ/w70k=; h=X-Yahoo-Newman-Id:X-Yahoo-Newman-Property:X-YMail-OSG:X-Yahoo-SMTP:Received:Subject:To:From:Date:Message-ID:User-Agent:MIME-Version:Content-Type:Content-Transfer-Encoding; b=I1TpsFYWlNRNNxm7L8TEJj6kvzlSfBS+IwSPjf3rq08TEl4acqG5NU2L8ur1yExGIEJhotlt8jNVFjYA9Lr+iOk+SnTbc0pE0TNVPkbH5w9D40lYLlkxNBMLupSW4VyvQlW8JN6zR/8+2QAEA6nuJPbap25N18cOI0ZhA6F75FU= X-Yahoo-Newman-Id: 368279.66479.bm@smtp107.mail.ird.yahoo.com X-Yahoo-Newman-Property: ymail-3 X-YMail-OSG: 1FklSLsVM1mlR6k2xk2y8emnKz4N0U4Iw3sZdjFwbnKilUe 2GlAdFR3jAjUASPtJYliO3slQ5wHInZX.p5uVDrGTcBccZ_lC3UexYz7wQ21 Hdnfe5hggK._w.gidIjlzdC3m81G0Vkp2SPPEes._MD6uy8a8SvkD2sCIEsx P95yd3LGPSOP09xYJ6i9oPlx.lG25_edYbmbRsjkqN8q5Q2PNdz7H7pKxQcm ASsBoZUQyiSMVj.mHqtJUyscB6I6a3lMHbtbuRvF3bzEnB_YLx1nsxx9bRgR ojausaxRXX8nSrDUd.FiJA9NwHvbT03H0C2ZnGVD17amGuPgqsqF20XHRGxh _UKc.rh5cltUIxpZjgewZIxb4v0XR4yrahISOmsYoat96ICXs0gdpZa06wg- - X-Yahoo-SMTP: RQd6UNeswBCQ2fC9eaSG0twUs6zySTuXUlUG9HuS_w-- Received: from localhost (aystarik@80.251.228.149 with plain) by smtp107.mail.ird.yahoo.com with SMTP; 14 Mar 2012 05:41:00 -0700 PDT To: qemu-devel@nongnu.org From: Alexey Starikovskiy Date: Wed, 14 Mar 2012 16:41:00 +0400 Message-ID: <20120314124100.5869.13685.stgit@x201> User-Agent: StGit/0.15 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 77.238.189.63 X-Mailman-Approved-At: Wed, 14 Mar 2012 09:37:51 -0400 Subject: [Qemu-devel] [PATCH v2 1/3] Add support for 64bit ARM system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Alexey Starikovskiy --- target-arm/cpu.h | 10 ++++------ target-arm/helper.c | 14 +++++++------- target-arm/machine.c | 16 ++++++---------- 3 files changed, 17 insertions(+), 23 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0d9b39c..0298a98 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -117,11 +117,9 @@ typedef struct CPUARMState { uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ - uint32_t c2_base0; /* MMU translation table base 0. */ - uint32_t c2_base1; /* MMU translation table base 1. */ + uint64_t c2_base0; /* MMU translation table base 0. */ + uint64_t c2_base1; /* MMU translation table base 1. */ uint32_t c2_control; /* MMU translation table base control. */ - uint32_t c2_mask; /* MMU translation table base selection mask. */ - uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ uint32_t c3; /* MMU domain access control register @@ -131,7 +129,7 @@ typedef struct CPUARMState { uint32_t c6_region[8]; /* MPU base/size registers. */ uint32_t c6_insn; /* Fault address registers. */ uint32_t c6_data; - uint32_t c7_par; /* Translation result. */ + uint64_t c7_par; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint32_t c9_pmcr; /* performance monitor control register */ @@ -455,7 +453,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 6 +#define CPU_SAVE_VERSION 7 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/helper.c b/target-arm/helper.c index abe1c30..d190104 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -325,7 +325,6 @@ void cpu_reset(CPUARMState *env) } } env->vfp.xregs[ARM_VFP_FPEXC] = 0; - env->cp15.c2_base_mask = 0xffffc000u; /* v7 performance monitor control register: same implementor * field as main ID register, and we implement no event counters. */ @@ -1050,12 +1049,15 @@ static inline int check_ap(CPUState *env, int ap, int domain_prot, static uint32_t get_level1_table_address(CPUState *env, uint32_t address) { uint32_t table; + int t0size = env->cp15.c2_control & 0x7; + uint32_t mask = ~(((uint32_t)0xffffffffu) >> t0size); - if (address & env->cp15.c2_mask) + if (address & mask) { table = env->cp15.c2_base1 & 0xffffc000; - else - table = env->cp15.c2_base0 & env->cp15.c2_base_mask; - + } else { + mask = ~((uint32_t)0x3fffu >> t0size); + table = env->cp15.c2_base0 & mask; + } table |= (address >> 18) & 0x3ffc; return table; } @@ -1531,8 +1533,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) case 2: val &= 7; env->cp15.c2_control = val; - env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val); - env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val); break; default: goto bad_reg; diff --git a/target-arm/machine.c b/target-arm/machine.c index f66b8df..8fa738e 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -27,11 +27,9 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->cp15.c1_coproc); qemu_put_be32(f, env->cp15.c1_xscaleauxcr); qemu_put_be32(f, env->cp15.c1_scr); - qemu_put_be32(f, env->cp15.c2_base0); - qemu_put_be32(f, env->cp15.c2_base1); + qemu_put_be64(f, env->cp15.c2_base0); + qemu_put_be64(f, env->cp15.c2_base1); qemu_put_be32(f, env->cp15.c2_control); - qemu_put_be32(f, env->cp15.c2_mask); - qemu_put_be32(f, env->cp15.c2_base_mask); qemu_put_be32(f, env->cp15.c2_data); qemu_put_be32(f, env->cp15.c2_insn); qemu_put_be32(f, env->cp15.c3); @@ -42,7 +40,7 @@ void cpu_save(QEMUFile *f, void *opaque) } qemu_put_be32(f, env->cp15.c6_insn); qemu_put_be32(f, env->cp15.c6_data); - qemu_put_be32(f, env->cp15.c7_par); + qemu_put_be64(f, env->cp15.c7_par); qemu_put_be32(f, env->cp15.c9_insn); qemu_put_be32(f, env->cp15.c9_data); qemu_put_be32(f, env->cp15.c9_pmcr); @@ -145,11 +143,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->cp15.c1_coproc = qemu_get_be32(f); env->cp15.c1_xscaleauxcr = qemu_get_be32(f); env->cp15.c1_scr = qemu_get_be32(f); - env->cp15.c2_base0 = qemu_get_be32(f); - env->cp15.c2_base1 = qemu_get_be32(f); + env->cp15.c2_base0 = qemu_get_be64(f); + env->cp15.c2_base1 = qemu_get_be64(f); env->cp15.c2_control = qemu_get_be32(f); - env->cp15.c2_mask = qemu_get_be32(f); - env->cp15.c2_base_mask = qemu_get_be32(f); env->cp15.c2_data = qemu_get_be32(f); env->cp15.c2_insn = qemu_get_be32(f); env->cp15.c3 = qemu_get_be32(f); @@ -160,7 +156,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) } env->cp15.c6_insn = qemu_get_be32(f); env->cp15.c6_data = qemu_get_be32(f); - env->cp15.c7_par = qemu_get_be32(f); + env->cp15.c7_par = qemu_get_be64(f); env->cp15.c9_insn = qemu_get_be32(f); env->cp15.c9_data = qemu_get_be32(f); env->cp15.c9_pmcr = qemu_get_be32(f);