From patchwork Wed Mar 14 08:26:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Starikovskiy X-Patchwork-Id: 146640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CF96EB6EE8 for ; Thu, 15 Mar 2012 02:42:47 +1100 (EST) Received: from localhost ([::1]:49541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7oPm-0000B3-5p for incoming@patchwork.ozlabs.org; Wed, 14 Mar 2012 09:38:54 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7jYH-000523-50 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 04:27:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7jXs-0001HE-8y for qemu-devel@nongnu.org; Wed, 14 Mar 2012 04:27:20 -0400 Received: from mail-bk0-f45.google.com ([209.85.214.45]:56098) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7jXr-0001GF-VA for qemu-devel@nongnu.org; Wed, 14 Mar 2012 04:26:56 -0400 Received: by mail-bk0-f45.google.com with SMTP id jg9so1280669bkc.4 for ; Wed, 14 Mar 2012 01:26:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=subject:to:from:date:message-id:in-reply-to:references:user-agent :mime-version:content-type:content-transfer-encoding; bh=vUFV/uBVqkIMhzTWsonLl70bYVSYcxv0FitWrkE+BHE=; b=VDNW9dDj0YeqfrGRW2rbsjk889EiYFmyNgqirGZm1ozf2PTAKThxA/L/s/odYGNEqQ ClBc0phxfB8k/oFnTz79aHAoBokN08oo83L788f4AHmDoSXfBplEvpF6qOVtQaV8tJd7 /nV0jhxqtOS75oJ3CJ3TrRLNnPjC/jAWgWvArcmcCfSp/fFogiTuf+Hev5bNiGnDKBQM lWpuOzBaualrvIHfgxMV/0mMMzIQSwsHhb6w8p1LPqCupxzZ3pscA503d3DQOVdXETLr CGPTWdQ7yb1BppE1wl4IQ9K3N7eTcE5LLLUv8lFnqzXgi/hS5uVhTLfeZY5mPXGtYOPj sNGA== Received: by 10.205.125.142 with SMTP id gs14mr613159bkc.95.1331713614929; Wed, 14 Mar 2012 01:26:54 -0700 (PDT) Received: from localhost ([80.251.228.149]) by mx.google.com with ESMTPS id je3sm6130367bkb.15.2012.03.14.01.26.54 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Mar 2012 01:26:54 -0700 (PDT) To: qemu-devel@nongnu.org From: Alexey Starikovskiy Date: Wed, 14 Mar 2012 12:26:53 +0400 Message-ID: <20120314082653.4923.70689.stgit@x201> In-Reply-To: <20120314082645.4923.21890.stgit@x201> References: <20120314082645.4923.21890.stgit@x201> User-Agent: StGit/0.15 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.214.45 X-Mailman-Approved-At: Wed, 14 Mar 2012 09:37:51 -0400 Subject: [Qemu-devel] [PATCH 2/3] Support for MRCC and MCRR instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Alexey Starikovskiy --- target-arm/helper.c | 28 ++++++++++++++++++++++++++++ target-arm/helper.h | 2 ++ target-arm/translate.c | 47 +++++++++++++++++++++++++++++------------------ 3 files changed, 59 insertions(+), 18 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index d190104..3c4c0e4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -670,6 +670,16 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) cpu_abort(env, "cp15 insn %08x\n", insn); } +void HELPER(set_cp15_64)(CPUState * env, uint32_t insn, uint64_t val) +{ + cpu_abort(env, "cp15 insn %08x\n", insn); +} + +uint64_t HELPER(get_cp15_64)(CPUState * env, uint32_t insn) +{ + cpu_abort(env, "cp15 insn %08x\n", insn); +} + /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) { @@ -2261,6 +2271,24 @@ bad_reg: return 0; } +void HELPER(set_cp15_64)(CPUState *env, uint32_t insn, uint64_t val) +{ + int crm = insn & 0xf; + int opc1 = (insn >> 4) & 0xf; + cpu_abort(env, "Unimplemented cp15 register 64bit write (c%d[%d])\n", + crm, opc1); +} + +uint64_t HELPER(get_cp15_64)(CPUState *env, uint32_t insn) +{ + /* Used for block cache operations, so just return 0 */ +#if 0 + cpu_abort(env, "Unimplemented cp15 register 64bit read (c%d[%d])\n", + crm, opc1); +#endif + return 0; +} + void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val) { if ((env->uncached_cpsr & CPSR_M) == mode) { diff --git a/target-arm/helper.h b/target-arm/helper.h index 16dd5fc..bc8151c 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -60,7 +60,9 @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) DEF_HELPER_3(set_cp15, void, env, i32, i32) +DEF_HELPER_3(set_cp15_64, void, env, i32, i64) DEF_HELPER_2(get_cp15, i32, env, i32) +DEF_HELPER_2(get_cp15_64, i64, env, i32) DEF_HELPER_3(set_cp, void, env, i32, i32) DEF_HELPER_2(get_cp, i32, env, i32) diff --git a/target-arm/translate.c b/target-arm/translate.c index 280bfca..27ba5fb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2559,17 +2559,9 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) /* M profile cores use memory mapped registers instead of cp15. */ if (arm_feature(env, ARM_FEATURE_M)) - return 1; + return 1; - if ((insn & (1 << 25)) == 0) { - if (insn & (1 << 20)) { - /* mrrc */ - return 1; - } - /* mcrr. Used for block cache operations, so implement as no-op. */ - return 0; - } - if ((insn & (1 << 4)) == 0) { + if ((insn & (1 << 4)) == 0 && (insn & (1 << 25))) { /* cdp */ return 1; } @@ -2636,16 +2628,35 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) tmp2 = tcg_const_i32(insn); if (insn & ARM_CP_RW_BIT) { - tmp = tcg_temp_new_i32(); - gen_helper_get_cp15(tmp, cpu_env, tmp2); - /* If the destination register is r15 then sets condition codes. */ - if (rd != 15) - store_reg(s, rd, tmp); - else - tcg_temp_free_i32(tmp); + if ((insn & (1 << 25))) { + tmp = tcg_temp_new_i32(); + gen_helper_get_cp15(tmp, cpu_env, tmp2); + /* If the destination register is r15 then sets condition codes. */ + if (rd != 15) { + store_reg(s, rd, tmp); + } else { + tcg_temp_free_i32(tmp); + } + } else { + int rd1 = (insn >> 16) & 0xf; + TCGv_i64 tmp1 = tcg_temp_new_i64(); + gen_helper_get_cp15_64(tmp1, cpu_env, tmp2); + tcg_gen_trunc_i64_i32(cpu_R[rd], tmp1); + tcg_gen_shri_i64(tmp1, tmp1, 32); + tcg_gen_trunc_i64_i32(cpu_R[rd1], tmp1); + tcg_temp_free_i64(tmp1); + } } else { tmp = load_reg(s, rd); - gen_helper_set_cp15(cpu_env, tmp2, tmp); + if ((insn & (1 << 25))) { + gen_helper_set_cp15(cpu_env, tmp2, tmp); + } else { + int rd1 = (insn >> 16) & 0xf; + TCGv_i64 tmp1 = tcg_temp_new_i64(); + tcg_gen_concat_i32_i64(tmp1, cpu_R[rd], cpu_R[rd1]); + gen_helper_set_cp15_64(cpu_env, tmp2, tmp1); + tcg_temp_free_i64(tmp1); + } tcg_temp_free_i32(tmp); /* Normally we would always end the TB here, but Linux * arch/arm/mach-pxa/sleep.S expects two instructions following