From patchwork Wed Jul 6 16:34:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Berger X-Patchwork-Id: 103539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 56A08B6F6B for ; Thu, 7 Jul 2011 03:05:27 +1000 (EST) Received: from localhost ([::1]:40704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QeVXQ-0003OS-0e for incoming@patchwork.ozlabs.org; Wed, 06 Jul 2011 13:05:24 -0400 Received: from eggs.gnu.org ([140.186.70.92]:38096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QeV5Q-00055i-8u for qemu-devel@nongnu.org; Wed, 06 Jul 2011 12:36:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QeV5O-0000Lx-K3 for qemu-devel@nongnu.org; Wed, 06 Jul 2011 12:36:28 -0400 Received: from e5.ny.us.ibm.com ([32.97.182.145]:36741) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QeV5O-0000Lt-Ba for qemu-devel@nongnu.org; Wed, 06 Jul 2011 12:36:26 -0400 Received: from d01relay05.pok.ibm.com (d01relay05.pok.ibm.com [9.56.227.237]) by e5.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id p66G7t3x014261 for ; Wed, 6 Jul 2011 12:07:55 -0400 Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d01relay05.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p66GaMfv160310 for ; Wed, 6 Jul 2011 12:36:24 -0400 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p66AYmkG005809 for ; Wed, 6 Jul 2011 04:34:48 -0600 Received: from localhost.localdomain (d941e-10.watson.ibm.com [9.59.241.154]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p66AYl3q005720 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 6 Jul 2011 04:34:47 -0600 Received: from localhost.localdomain (d941e-10 [127.0.0.1]) by localhost.localdomain (8.14.4/8.14.3) with ESMTP id p66GZEGe026481; Wed, 6 Jul 2011 12:35:14 -0400 Received: (from root@localhost) by localhost.localdomain (8.14.4/8.14.4/Submit) id p66GZEcC026480; Wed, 6 Jul 2011 12:35:14 -0400 Message-Id: <20110706163514.306201274@linux.vnet.ibm.com> User-Agent: quilt/0.48-1 Date: Wed, 06 Jul 2011 12:34:45 -0400 From: Stefan Berger To: stefanb@linux.vnet.ibm.com, qemu-devel@nongnu.org References: <20110706163440.987096936@linux.vnet.ibm.com> Content-Disposition: inline; filename=qemu_tpm_tis_debugreg.diff X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 32.97.182.145 Cc: anbang.ruan@cs.ox.ac.uk, andreas.niederl@iaik.tugraz.at, serge@hallyn.com Subject: [Qemu-devel] [PATCH V6 05/13] Add a debug register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch uses the possibility to add a vendor-specific register and adds a debug register useful for dumping the TIS's internal state. This register is only active in a debug build (#define DEBUG_TIS). v3: - all output goes to stderr Signed-off-by: Stefan Berger --- hw/tpm_tis.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) Index: qemu-git/hw/tpm_tis.c =================================================================== --- qemu-git.orig/hw/tpm_tis.c +++ qemu-git/hw/tpm_tis.c @@ -43,6 +43,8 @@ #define TIS_REG_DID_VID 0xf00 #define TIS_REG_RID 0xf04 +/* vendor-specific registers */ +#define TIS_REG_DEBUG 0xf90 #define STS_VALID (1 << 7) #define STS_COMMAND_READY (1 << 6) @@ -316,6 +318,66 @@ static uint32_t tis_data_read(TPMState * } +#ifdef DEBUG_TIS +static void tis_dump_state(void *opaque, target_phys_addr_t addr) +{ + static const unsigned regs[] = { + TIS_REG_ACCESS, + TIS_REG_INT_ENABLE, + TIS_REG_INT_VECTOR, + TIS_REG_INT_STATUS, + TIS_REG_INTF_CAPABILITY, + TIS_REG_STS, + TIS_REG_DID_VID, + TIS_REG_RID, + 0xfff}; + int idx; + uint8_t locty = tis_locality_from_addr(addr); + target_phys_addr_t base = addr & ~0xfff; + TPMState *s = opaque; + + fprintf(stderr, + "tpm_tis: active locality : %d\n" + "tpm_tis: state of locality %d : %d\n" + "tpm_tis: register dump:\n", + s->active_locty, + locty, s->loc[locty].state); + + for (idx = 0; regs[idx] != 0xfff; idx++) { + fprintf(stderr, "tpm_tis: 0x%04x : 0x%08x\n", regs[idx], + tis_mem_readl(opaque, base + regs[idx])); + } + + fprintf(stderr, + "tpm_tis: read offset : %d\n" + "tpm_tis: result buffer : ", + s->loc[locty].r_offset); + for (idx = 0; + idx < tis_get_size_from_buffer(&s->loc[locty].r_buffer); + idx++) { + fprintf(stderr, "%c%02x%s", + s->loc[locty].r_offset == idx ? '>' : ' ', + s->loc[locty].r_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + fprintf(stderr, + "\n" + "tpm_tis: write offset : %d\n" + "tpm_tis: request buffer: ", + s->loc[locty].w_offset); + for (idx = 0; + idx < tis_get_size_from_buffer(&s->loc[locty].w_buffer); + idx++) { + fprintf(stderr, "%c%02x%s", + s->loc[locty].w_offset == idx ? '>' : ' ', + s->loc[locty].w_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + fprintf(stderr,"\n"); +} +#endif + + /* * Read a register of the TIS interface * See specs pages 33-63 for description of the registers @@ -391,6 +453,11 @@ static uint32_t tis_mem_readl(void *opaq case TIS_REG_RID: val = TPM_RID; break; +#ifdef DEBUG_TIS + case TIS_REG_DEBUG: + tis_dump_state(opaque, addr); + break; +#endif } qemu_mutex_unlock(&s->state_lock);