From patchwork Wed Jun 2 19:38:45 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Igor V. Kovalenko" X-Patchwork-Id: 54423 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 95195B7D1F for ; Thu, 3 Jun 2010 05:55:43 +1000 (EST) Received: from localhost ([127.0.0.1]:58554 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OJu2N-0000mI-N3 for incoming@patchwork.ozlabs.org; Wed, 02 Jun 2010 15:55:39 -0400 Received: from [140.186.70.92] (port=32880 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OJtm6-00040b-C4 for qemu-devel@nongnu.org; Wed, 02 Jun 2010 15:38:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OJtm4-0003ZC-Lg for qemu-devel@nongnu.org; Wed, 02 Jun 2010 15:38:50 -0400 Received: from mail-fx0-f45.google.com ([209.85.161.45]:42583) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OJtm4-0003Z3-D6 for qemu-devel@nongnu.org; Wed, 02 Jun 2010 15:38:48 -0400 Received: by fxm17 with SMTP id 17so5157319fxm.4 for ; Wed, 02 Jun 2010 12:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:subject:to:from:date :message-id:user-agent:mime-version:content-type :content-transfer-encoding; bh=aUFo+MSx6EKJgzPKiMASYT7u/EanzVSTxUSmOz+lv9E=; b=LvCuQmjmFwSZ5XZRCbMw4ydBgXUng+oML+PeG3e5U47/r5KO8oVFjZjzJBgzGTYz3t /oP17VapYsMpquX7do383FGhcAeQiNJuD7piSJTigU0UvuIA6wtvY0CpLAQbsNa91YWX K0ics9JD3cDXmAM+dVf0fN412VEQ96EUlzSbI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:to:from:date:message-id:user-agent:mime-version :content-type:content-transfer-encoding; b=RmQ0YY+YXFJwDPhVg35RgUWCAPMcPhoxQk/oOL9SFSoXNXjPLxoTl8IqTeRw/l2vmX ZKrsxTV0SxS1e8Va75Q+Ir1/Tm97neK83aXqdhTwsCAj5A3gmxV2aUba5aimA910FESQ MSftiUdrwmCV8oDcwShkMG4FFB0ZxQoNOMrq0= Received: by 10.223.24.5 with SMTP id t5mr9149906fab.72.1275507527163; Wed, 02 Jun 2010 12:38:47 -0700 (PDT) Received: from skyserv ([87.255.14.75]) by mx.google.com with ESMTPS id j23sm53677502faa.14.2010.06.02.12.38.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 02 Jun 2010 12:38:46 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=[192.168.1.2]) by skyserv with esmtp (Exim 4.71) (envelope-from ) id 1OJtm1-0005Nu-Kh for qemu-devel@nongnu.org; Wed, 02 Jun 2010 23:38:45 +0400 To: qemu-devel@nongnu.org From: "Igor V. Kovalenko" Date: Wed, 02 Jun 2010 23:38:45 +0400 Message-ID: <20100602193845.20678.94499.stgit@skyserv> User-Agent: StGit/0.15 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH] sparc64: fix missing address masking v1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Igor V. Kovalenko - address masking for ldqf and stqf insns - address masking for lddf and stdf insns - address masking for translating ASI (Ultrasparc IIi) v0->v1: - move arch-specific code to helpers and drop more ifdefs at call sites using new helper asi_address_mask() - change user emulation to use asi_address_mask() Signed-off-by: Igor V. Kovalenko --- target-sparc/op_helper.c | 50 ++++++++++++++++++++++++++++++++++++++++++++-- target-sparc/translate.c | 4 ++++ 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index ef3504f..f5e4633 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -247,6 +247,42 @@ static inline target_ulong address_mask(CPUState *env1, target_ulong addr) return addr; } +/* returns true if access using this ASI is to have address translated by MMU + otherwise access is to raw physical address */ +static inline int is_translating_asi(int asi) +{ +#ifdef TARGET_SPARC64 + /* Ultrasparc IIi translating asi + - note this list is defined by cpu implementation + */ + switch (asi) { + case 0x04 ... 0x11: + case 0x18 ... 0x19: + case 0x24 ... 0x2C: + case 0x70 ... 0x73: + case 0x78 ... 0x79: + case 0x80 ... 0xFF: + return 1; + + default: + return 0; + } +#else + /* TODO: check sparc32 bits */ + return 0; +#endif +} + +static inline target_ulong asi_address_mask(CPUState *env1, + int asi, target_ulong addr) +{ + if (is_translating_asi(asi)) { + return address_mask(env, addr); + } else { + return addr; + } +} + static void raise_exception(int tt) { env->exception_index = tt; @@ -2151,7 +2187,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) raise_exception(TT_PRIV_ACT); helper_check_align(addr, size - 1); - addr = address_mask(env, addr); + addr = asi_address_mask(env, asi, addr); switch (asi) { case 0x82: // Primary no-fault @@ -2254,7 +2290,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) raise_exception(TT_PRIV_ACT); helper_check_align(addr, size - 1); - addr = address_mask(env, addr); + addr = asi_address_mask(env, asi, addr); /* Convert to little endian */ switch (asi) { @@ -2331,6 +2367,8 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) raise_exception(TT_PRIV_ACT); helper_check_align(addr, size - 1); + addr = asi_address_mask(env, asi, addr); + switch (asi) { case 0x82: // Primary no-fault case 0x8a: // Primary no-fault LE @@ -2682,6 +2720,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) raise_exception(TT_PRIV_ACT); helper_check_align(addr, size - 1); + addr = asi_address_mask(env, asi, addr); + /* Convert to little endian */ switch (asi) { case 0x0c: // Nucleus Little Endian (LE) @@ -3056,6 +3096,8 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd) && !(env->hpstate & HS_PRIV))) raise_exception(TT_PRIV_ACT); + addr = asi_address_mask(env, asi, addr); + switch (asi) { #if !defined(CONFIG_USER_ONLY) case 0x24: // Nucleus quad LDD 128 bit atomic @@ -3103,6 +3145,8 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) target_ulong val; helper_check_align(addr, 3); + addr = asi_address_mask(env, asi, addr); + switch (asi) { case 0xf0: // Block load primary case 0xf1: // Block load secondary @@ -3145,6 +3189,8 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd) target_ulong val = 0; helper_check_align(addr, 3); + addr = asi_address_mask(env, asi, addr); + switch (asi) { case 0xe0: // UA2007 Block commit store primary (cache flush) case 0xe1: // UA2007 Block commit store secondary (cache flush) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 72ca0b4..eff64d4 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -4490,6 +4490,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_ldqf(cpu_addr, r_const); tcg_temp_free_i32(r_const); gen_op_store_QT0_fpr(QFPREG(rd)); @@ -4500,6 +4501,7 @@ static void disas_sparc_insn(DisasContext * dc) TCGv_i32 r_const; r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_lddf(cpu_addr, r_const); tcg_temp_free_i32(r_const); gen_op_store_DT0_fpr(DFPREG(rd)); @@ -4635,6 +4637,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT0(QFPREG(rd)); r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_stqf(cpu_addr, r_const); tcg_temp_free_i32(r_const); } @@ -4657,6 +4660,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rd)); r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_stdf(cpu_addr, r_const); tcg_temp_free_i32(r_const); }