From patchwork Wed Nov 25 11:39:11 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 39308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 66E2BB7B69 for ; Wed, 25 Nov 2009 22:50:46 +1100 (EST) Received: from localhost ([127.0.0.1]:57299 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDGOR-00018l-4L for incoming@patchwork.ozlabs.org; Wed, 25 Nov 2009 06:50:43 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NDGFw-0006Xk-KZ for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:56 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NDGFr-0006UP-Db for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:55 -0500 Received: from [199.232.76.173] (port=54745 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDGFq-0006U1-QT for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:50 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45886) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NDGFq-00014z-7w for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:50 -0500 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id nAPBfmvR010304 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 25 Nov 2009 06:41:48 -0500 Received: from redhat.com (vpn2-8-64.ams2.redhat.com [10.36.8.64]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id nAPBfkWO003266; Wed, 25 Nov 2009 06:41:47 -0500 Date: Wed, 25 Nov 2009 13:39:11 +0200 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org, anthony@codemonkey.ws Message-ID: <20091125113911.GD9322@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Cc: Subject: [Qemu-devel] [PATCH 3/5] msix: macro rename for function mask support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org rename ENABLE_OFFSET -> CONTROL_OFFSET, since same byte includes function mask. This is in preparation for function mask support. Signed-off-by: Michael S. Tsirkin --- hw/msix.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/msix.c b/hw/msix.c index 785e097..07111d0 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -27,8 +27,8 @@ #define MSIX_PBA_OFFSET 8 #define MSIX_CAP_LENGTH 12 -/* MSI enable bit is in byte 1 in FLAGS register */ -#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */ +#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1) #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) /* MSI-X table format */ @@ -101,7 +101,7 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, bar_nr); pdev->msix_cap = config_offset; /* Make flags bit writeable. */ - pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK; + pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK; return 0; } @@ -117,7 +117,7 @@ static void msix_free_irq_entries(PCIDevice *dev) void msix_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len) { - unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET; + unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET; if (addr + len <= enable_pos || addr > enable_pos) return; @@ -325,7 +325,7 @@ int msix_present(PCIDevice *dev) int msix_enabled(PCIDevice *dev) { return (dev->cap_present & QEMU_PCI_CAP_MSIX) && - (dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] & + (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_ENABLE_MASK); } @@ -361,8 +361,8 @@ void msix_reset(PCIDevice *dev) if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) return; msix_free_irq_entries(dev); - dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= - ~dev->wmask[dev->msix_cap + MSIX_ENABLE_OFFSET]; + dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &= + ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE); msix_mask_all(dev, dev->msix_entries_nr); }