From patchwork Wed Sep 23 20:06:35 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 34190 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 39F99B7B75 for ; Thu, 24 Sep 2009 06:09:28 +1000 (EST) Received: from localhost ([127.0.0.1]:46789 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MqY9V-000814-5z for incoming@patchwork.ozlabs.org; Wed, 23 Sep 2009 16:09:25 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MqY8o-0007zh-2R for qemu-devel@nongnu.org; Wed, 23 Sep 2009 16:08:42 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MqY8i-0007wU-Vp for qemu-devel@nongnu.org; Wed, 23 Sep 2009 16:08:41 -0400 Received: from [199.232.76.173] (port=54895 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MqY8i-0007wP-Jg for qemu-devel@nongnu.org; Wed, 23 Sep 2009 16:08:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:29364) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MqY8h-0002LT-Pe for qemu-devel@nongnu.org; Wed, 23 Sep 2009 16:08:36 -0400 Received: from int-mx08.intmail.prod.int.phx2.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.21]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n8NK8Vpo019384; Wed, 23 Sep 2009 16:08:31 -0400 Received: from redhat.com (vpn-10-24.str.redhat.com [10.32.10.24]) by int-mx08.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id n8NK8OeB005060 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NO); Wed, 23 Sep 2009 16:08:28 -0400 Date: Wed, 23 Sep 2009 23:06:35 +0300 From: "Michael S. Tsirkin" To: Blue Swirl Message-ID: <20090923200635.GA21246@redhat.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.19 (2009-01-05) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.21 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCHv2] qemu: target library, use it in msix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This creates target.c, which builds per-target, and makes it possible for devices to become target-independent. Use it in msix, reverting part of 5e520a7d500ec2569d22d80f9ef4272a34cb3c80, as we no longer have to pass target page around. Signed-off-by: Michael S. Tsirkin --- Makefile.target | 3 +++ hw/msix.c | 51 ++++++++++++++++++++++++++------------------------- hw/msix.h | 5 ++--- hw/pci.h | 6 ------ hw/virtio-pci.c | 3 +-- target.c | 17 +++++++++++++++++ target.h | 6 ++++++ 7 files changed, 55 insertions(+), 36 deletions(-) create mode 100644 target.c create mode 100644 target.h diff --git a/Makefile.target b/Makefile.target index 0ebef17..c0f143a 100644 --- a/Makefile.target +++ b/Makefile.target @@ -55,6 +55,9 @@ libobj-$(CONFIG_S390_DIS) += s390-dis.o libobj-$(CONFIG_SH4_DIS) += sh4-dis.o libobj-$(CONFIG_SPARC_DIS) += sparc-dis.o +# Target library: makes devices target-independent +libobj-y += target.o + # libqemu libqemu.a: $(libobj-y) diff --git a/hw/msix.c b/hw/msix.c index 3782994..af820ec 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -14,6 +14,7 @@ #include "hw.h" #include "msix.h" #include "pci.h" +#include "target.h" /* Declaration from linux/pci_regs.h */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ @@ -38,6 +39,15 @@ #define MSIX_VECTOR_CTRL 12 #define MSIX_ENTRY_SIZE 16 #define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requires giving the table structure + * a 4K aligned region all by itself. Align it to + * target pages so that drivers can do passthrough + * on the rest of the region. */ +#define MSIX_PAGE_SIZE target_page_align(0x1000) +/* Reserve second half of the page for pending bits */ +#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2) #define MSIX_MAX_ENTRIES 32 @@ -53,12 +63,6 @@ /* Flag for interrupt controller to declare MSI-X support */ int msix_supported; -/* Reserve second half of the page for pending bits */ -static int msix_page_pending(PCIDevice *d) -{ - return (d->msix_page_size / 2); -} - /* Add MSI-X capability to the config space for the device. */ /* Given a bar and its size, add MSI-X table on top of it * and fill MSI-X capability in the config space. @@ -77,11 +81,11 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, return -ENOSPC; /* Add space for MSI-X structures */ - if (!bar_size) { - new_size = pdev->msix_page_size; - } else if (bar_size < pdev->msix_page_size) { - bar_size = pdev->msix_page_size; - new_size = pdev->msix_page_size * 2; + if (!bar_size) + new_size = MSIX_PAGE_SIZE; + else if (bar_size < MSIX_PAGE_SIZE) { + bar_size = MSIX_PAGE_SIZE; + new_size = MSIX_PAGE_SIZE * 2; } else new_size = bar_size * 2; @@ -95,8 +99,8 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, /* Table on top of BAR */ pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr); /* Pending bits on top of that */ - pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + msix_page_pending(pdev)) - | bar_nr); + pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) | + bar_nr); pdev->msix_cap = config_offset; /* Make flags bit writeable. */ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK; @@ -126,7 +130,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr, static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr) { PCIDevice *dev = opaque; - unsigned int offset = addr & (dev->msix_page_size - 1); + unsigned int offset = addr & (MSIX_PAGE_SIZE - 1); void *page = dev->msix_table_page; uint32_t val = 0; @@ -148,7 +152,7 @@ static uint8_t msix_pending_mask(int vector) static uint8_t *msix_pending_byte(PCIDevice *dev, int vector) { - return dev->msix_table_page + msix_page_pending(dev) + vector / 8; + return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8; } static int msix_is_pending(PCIDevice *dev, int vector) @@ -176,7 +180,7 @@ static void msix_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { PCIDevice *dev = opaque; - unsigned int offset = addr & (dev->msix_page_size - 1); + unsigned int offset = addr & (MSIX_PAGE_SIZE - 1); int vector = offset / MSIX_ENTRY_SIZE; memcpy(dev->msix_table_page + offset, &val, 4); if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) { @@ -205,7 +209,7 @@ void msix_mmio_map(PCIDevice *d, int region_num, { uint8_t *config = d->config + d->msix_cap; uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET); - uint32_t offset = table & ~(d->msix_page_size - 1); + uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1); /* TODO: for assigned devices, we'll want to make it possible to map * pending bits separately in case they are in a separate bar. */ int table_bir = table & PCI_MSIX_FLAGS_BIRMASK; @@ -221,7 +225,7 @@ void msix_mmio_map(PCIDevice *d, int region_num, /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is * modified, it should be retrieved with msix_bar_size. */ int msix_init(struct PCIDevice *dev, unsigned short nentries, - unsigned bar_nr, unsigned bar_size, target_phys_addr_t page_size) + unsigned bar_nr, unsigned bar_size) { int ret; /* Nothing to do if MSI is not supported by interrupt controller */ @@ -234,8 +238,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES * sizeof *dev->msix_entry_used); - dev->msix_page_size = page_size; - dev->msix_table_page = qemu_mallocz(dev->msix_page_size); + dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE); dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read, msix_mmio_write, dev); @@ -290,8 +293,7 @@ void msix_save(PCIDevice *dev, QEMUFile *f) } qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE); - qemu_put_buffer(f, dev->msix_table_page + msix_page_pending(dev), - (n + 7) / 8); + qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); } /* Should be called after restoring the config space. */ @@ -305,8 +307,7 @@ void msix_load(PCIDevice *dev, QEMUFile *f) msix_free_irq_entries(dev); qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE); - qemu_get_buffer(f, dev->msix_table_page + msix_page_pending(dev), - (n + 7) / 8); + qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); } /* Does device support MSI-X? */ @@ -356,7 +357,7 @@ void msix_reset(PCIDevice *dev) return; msix_free_irq_entries(dev); dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK; - memset(dev->msix_table_page, 0, dev->msix_page_size); + memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE); } /* PCI spec suggests that devices make it possible for software to configure diff --git a/hw/msix.h b/hw/msix.h index 9367ba3..3427778 100644 --- a/hw/msix.h +++ b/hw/msix.h @@ -3,9 +3,8 @@ #include "qemu-common.h" -int msix_init(struct PCIDevice *dev, unsigned short nentries, - unsigned bar_nr, unsigned bar_size, - target_phys_addr_t page_size); +int msix_init(PCIDevice *pdev, unsigned short nentries, + unsigned bar_nr, unsigned bar_size); void msix_write_config(PCIDevice *pci_dev, uint32_t address, uint32_t val, int len); diff --git a/hw/pci.h b/hw/pci.h index dddd599..8cfc38d 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -214,12 +214,6 @@ struct PCIDevice { uint32_t msix_bar_size; /* Version id needed for VMState */ int32_t version_id; - /* How much space does an MSIX table need. */ - /* The spec requires giving the table structure - * a 4K aligned region all by itself. Align it to - * target pages so that drivers can do passthrough - * on the rest of the region. */ - target_phys_addr_t msix_page_size; }; PCIDevice *pci_register_device(PCIBus *bus, const char *name, diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c index 1f14c5e..3a0231e 100644 --- a/hw/virtio-pci.c +++ b/hw/virtio-pci.c @@ -410,8 +410,7 @@ static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev, config[0x3d] = 1; - if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0, - TARGET_PAGE_SIZE)) { + if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) { pci_register_bar(&proxy->pci_dev, 1, msix_bar_size(&proxy->pci_dev), PCI_ADDRESS_SPACE_MEM, diff --git a/target.c b/target.c new file mode 100644 index 0000000..3287eea --- /dev/null +++ b/target.c @@ -0,0 +1,17 @@ +/* + * Target definitions for use by devices. + * + * Author: Michael S. Tsirkin + * + * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com) + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ +#include "qemu-common.h" +#include "target.h" + +unsigned target_page_align(unsigned value) +{ + return TARGET_PAGE_ALIGN(value); +} diff --git a/target.h b/target.h new file mode 100644 index 0000000..0e01e47 --- /dev/null +++ b/target.h @@ -0,0 +1,6 @@ +#ifndef QEMU_TARGET_H +#define QEMU_TARGET_H + +unsigned target_page_align(unsigned value); + +#endif