From patchwork Wed Sep 16 10:40:57 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 33700 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 10438B7B3E for ; Wed, 16 Sep 2009 20:51:41 +1000 (EST) Received: from localhost ([127.0.0.1]:58980 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mns6r-0005BO-F1 for incoming@patchwork.ozlabs.org; Wed, 16 Sep 2009 06:51:37 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MnryX-0001Sm-OD for qemu-devel@nongnu.org; Wed, 16 Sep 2009 06:43:01 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MnryS-0001M1-J1 for qemu-devel@nongnu.org; Wed, 16 Sep 2009 06:43:01 -0400 Received: from [199.232.76.173] (port=37515 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MnryS-0001Li-DA for qemu-devel@nongnu.org; Wed, 16 Sep 2009 06:42:56 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50122) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MnryR-0007IJ-Lc for qemu-devel@nongnu.org; Wed, 16 Sep 2009 06:42:56 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n8GAgiX7024338; Wed, 16 Sep 2009 06:42:45 -0400 Received: from redhat.com (dhcp-0-94.tlv.redhat.com [10.35.0.94]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id n8GAgaDl030683 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NO); Wed, 16 Sep 2009 06:42:41 -0400 Date: Wed, 16 Sep 2009 13:40:57 +0300 From: "Michael S. Tsirkin" To: Paul Brook , Avi Kivity , qemu-devel@nongnu.org, Carsten Otte , Christian Borntraeger , kraxel@redhat.com, markmc@redhat.com Message-ID: <20090916104057.GD4446@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Cc: Subject: [Qemu-devel] [PATCHv2 3/4] qemu/pci: refactor code/symbolic constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org refactor code slightly, adding symbolic constants and functions, and using macros where possible. This will also make following reset patches easier. No functional changes. Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 41 +++++++++++++++++++++-------------------- hw/pci.h | 2 ++ 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index c12b0be..600df2f 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -83,6 +83,16 @@ static const VMStateDescription vmstate_pcibus = { } }; +static inline int pci_bar(int reg) +{ + return reg == PCI_ROM_SLOT ? PCI_ROM_ADDRESS : PCI_BASE_ADDRESS_0 + reg * 4; +} + +static void pci_device_reset(PCIDevice *dev) +{ + memset(dev->irq_state, 0, sizeof dev->irq_state); +} + static void pci_bus_reset(void *opaque) { PCIBus *bus = opaque; @@ -91,10 +101,10 @@ static void pci_bus_reset(void *opaque) for (i = 0; i < bus->nirq; i++) { bus->irq_count[i] = 0; } - for (i = 0; i < 256; i++) { - if (bus->devices[i]) - memset(bus->devices[i]->irq_state, 0, - sizeof(bus->devices[i]->irq_state)); + for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { + if (bus->devices[i]) { + pci_device_reset(bus->devices[i]); + } } } @@ -419,12 +429,10 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, r->map_func = map_func; wmask = ~(size - 1); + addr = pci_bar(region_num); if (region_num == PCI_ROM_SLOT) { - addr = 0x30; /* ROM enable bit is writeable */ - wmask |= 1; - } else { - addr = 0x10 + region_num * 4; + wmask |= PCI_ROM_ADDRESS_ENABLE; } *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); @@ -435,21 +443,15 @@ static void pci_update_mappings(PCIDevice *d) { PCIIORegion *r; int cmd, i; - uint32_t last_addr, new_addr, config_ofs; + uint32_t last_addr, new_addr; cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); for(i = 0; i < PCI_NUM_REGIONS; i++) { r = &d->io_regions[i]; - if (i == PCI_ROM_SLOT) { - config_ofs = 0x30; - } else { - config_ofs = 0x10 + i * 4; - } if (r->size != 0) { if (r->type & PCI_ADDRESS_SPACE_IO) { if (cmd & PCI_COMMAND_IO) { - new_addr = le32_to_cpu(*(uint32_t *)(d->config + - config_ofs)); + new_addr = pci_get_long(d->config + pci_bar(i)); new_addr = new_addr & ~(r->size - 1); last_addr = new_addr + r->size - 1; /* NOTE: we have only 64K ioports on PC */ @@ -462,10 +464,9 @@ static void pci_update_mappings(PCIDevice *d) } } else { if (cmd & PCI_COMMAND_MEMORY) { - new_addr = le32_to_cpu(*(uint32_t *)(d->config + - config_ofs)); + new_addr = pci_get_long(d->config + pci_bar(i)); /* the ROM slot has a specific enable bit */ - if (i == PCI_ROM_SLOT && !(new_addr & 1)) + if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) goto no_mem_map; new_addr = new_addr & ~(r->size - 1); last_addr = new_addr + r->size - 1; @@ -489,7 +490,7 @@ static void pci_update_mappings(PCIDevice *d) int class; /* NOTE: specific hack for IDE in PC case: only one byte must be mapped. */ - class = d->config[0x0a] | (d->config[0x0b] << 8); + class = pci_get_word(d->config + PCI_CLASS_DEVICE); if (class == 0x0101 && r->size == 4) { isa_unassign_ioport(r->addr + 2, 1); } else { diff --git a/hw/pci.h b/hw/pci.h index 6196b6a..5481757 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -117,6 +117,8 @@ typedef struct PCIIORegion { #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */