From patchwork Tue May 21 06:34:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 245211 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 42EDC2C0087 for ; Tue, 21 May 2013 16:45:24 +1000 (EST) Received: from localhost ([::1]:41849 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegK2-00020J-HF for incoming@patchwork.ozlabs.org; Tue, 21 May 2013 02:45:22 -0400 Received: from eggs.gnu.org ([208.118.235.92]:53928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegJl-0001xB-Hs for qemu-devel@nongnu.org; Tue, 21 May 2013 02:45:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UegJk-00081A-46 for qemu-devel@nongnu.org; Tue, 21 May 2013 02:45:05 -0400 Received: from mail-pb0-x22a.google.com ([2607:f8b0:400e:c01::22a]:44358) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegJj-0007zD-Sh for qemu-devel@nongnu.org; Tue, 21 May 2013 02:45:04 -0400 Received: by mail-pb0-f42.google.com with SMTP id uo1so299248pbc.1 for ; Mon, 20 May 2013 23:45:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=8Vhj/t78Y60FPCKXPAN0bWpK8TKMqjcL/sN30/KXkS8=; b=EtibjMM7XfHEfGqK4vcDRFHHsehAj2nVFa1sEmSFQPfTY2Frf8emPbZ9FqF2nrg7xQ lysokTP4cBFqorGwqg7rrq0dxjqSbEJZsiQxcwO950GBldqOt+P00GzzWcN1UsXH4sF6 vpvcPUeG7X2qIlERS3sEgX4RQEIStjIaN02CmklM7QzXg2/fHzHw8CiXeGte0olXZn9O Cz+4QY4wleQgZuAscZcI8nWIvW0g/2tyPPEtKevFtCPm0A/tmsZUEIaXZ/UTNQh52u58 wEcEghaKMqRpqjQeLXIlaQDcKFwd0bdCVnLTHUoQL82foNeKWpAKhkNJB2ZXzpDbozl9 Ekaw== X-Received: by 10.68.204.98 with SMTP id kx2mr1225820pbc.26.1369118324458; Mon, 20 May 2013 23:38:44 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id ra4sm2009754pab.9.2013.05.20.23.38.40 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 20 May 2013 23:38:43 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Tue, 21 May 2013 16:34:25 +1000 Message-Id: <1d67383adc42761af715a93f161344b9284dfc9a.1369117359.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQkpsJFy8Ta5PnfwWWKxE1jFVR0njSwaTi9mE7FE+qN1mLQI6+cYCyrLF7mKuel66Vzb9qYj X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::22a Cc: edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH arm-devs v4 08/15] xilinx_spips: Implement automatic CS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Implement the automatic CS control feature. If the MANUAL_CS bit is cleared then the chip select stay de-asserted as long as the tx FIFO is empty. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- changed from v3: remove usage on DB_PRINT_L (PMM review) changed from v1: Refresh CS on entry and exit from flush routine as needed. hw/ssi/xilinx_spips.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 0c04ec9..631d010 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -190,6 +190,12 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } +static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) +{ + return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS + || !fifo8_is_empty(&s->tx_fifo)); +} + static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) { int i, j; @@ -202,14 +208,15 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) int cs_to_set = (j * s->num_cs + i + upage) % (s->num_cs * s->num_busses); - if (~field & (1 << i) && !found) { + if (xilinx_spips_cs_is_set(s, i, field) && !found) { DB_PRINT("selecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 0); } else { + DB_PRINT("deselecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 1); } } - if (~field & (1 << i)) { + if (xilinx_spips_cs_is_set(s, i, field)) { found = true; } } @@ -451,12 +458,13 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: + xilinx_spips_update_cs_lines(s); if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { xilinx_spips_flush_txfifo(s); } - xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); + xilinx_spips_update_ixr(s); } static const MemoryRegionOps spips_ops = { @@ -510,7 +518,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) fifo8_reset(&s->rx_fifo); s->regs[R_CONFIG] &= ~CS; - s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS; + s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS; xilinx_spips_update_cs_lines(s); /* instruction */ @@ -534,6 +542,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) DB_PRINT("pushing dummy byte\n"); fifo8_push(&s->tx_fifo, 0); } + xilinx_spips_update_cs_lines(s); xilinx_spips_flush_txfifo(s); fifo8_reset(&s->rx_fifo); @@ -545,6 +554,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4); cache_entry++; } + xilinx_spips_update_cs_lines(s); s->regs[R_CONFIG] |= CS; xilinx_spips_update_cs_lines(s);