From patchwork Wed Nov 5 09:02:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hu Tao X-Patchwork-Id: 406916 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 95CB4140098 for ; Wed, 5 Nov 2014 20:10:11 +1100 (AEDT) Received: from localhost ([::1]:45201 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlwbR-0007mr-Ms for incoming@patchwork.ozlabs.org; Wed, 05 Nov 2014 04:10:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47630) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlwXg-0001bJ-V4 for qemu-devel@nongnu.org; Wed, 05 Nov 2014 04:06:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlwXa-0004mi-2p for qemu-devel@nongnu.org; Wed, 05 Nov 2014 04:06:16 -0500 Received: from [59.151.112.132] (port=5748 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlwXZ-0004lu-Gf for qemu-devel@nongnu.org; Wed, 05 Nov 2014 04:06:10 -0500 X-IronPort-AV: E=Sophos;i="5.04,848,1406563200"; d="scan'208";a="42885675" Received: from unknown (HELO edo.cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 05 Nov 2014 17:02:58 +0800 Received: from G08CNEXCHPEKD03.g08.fujitsu.local (localhost.localdomain [127.0.0.1]) by edo.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id sA595v9B028050; Wed, 5 Nov 2014 17:05:58 +0800 Received: from localhost.localdomain (10.167.226.102) by G08CNEXCHPEKD03.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.181.6; Wed, 5 Nov 2014 17:06:11 +0800 From: Hu Tao To: Date: Wed, 5 Nov 2014 17:02:46 +0800 Message-ID: <1a921f0dd4882ce750c8442471e16751deebec1c.1415177705.git.hutao@cn.fujitsu.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.226.102] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Cc: "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [Qemu-devel] [PATCH v2 5/5] pci: remove the limit parameter of pci_host_config_write_common X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since the limit parameter is always set to the size of pci device's configuration space, and we can determine the size from the type of pci device. Signed-off-by: Hu Tao --- hw/pci/pci_host.c | 13 ++++++++++--- hw/pci/pcie_host.c | 9 +-------- hw/ppc/spapr_pci.c | 3 +-- include/hw/pci/pci_host.h | 2 +- 4 files changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 2b11551..4a59b0e 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -49,8 +49,16 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr) } void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, - uint32_t limit, uint32_t val, uint32_t len) + uint32_t val, uint32_t len) { + uint32_t limit = pci_config_size(pci_dev); + + if (limit <= addr) { + /* conventional pci device can be behind pcie-to-pci bridge. + 256 <= addr < 4K has no effects. */ + return; + } + assert(len <= 4); trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn), addr, val); @@ -89,8 +97,7 @@ void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len) PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n", __func__, pci_dev->name, config_addr, val, len); - pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE, - val, len); + pci_host_config_write_common(pci_dev, config_addr, val, len); } uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index cf8587b..e3a2a80 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -39,19 +39,12 @@ static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr, PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); uint32_t addr; - uint32_t limit; if (!pci_dev) { return; } addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr); - limit = pci_config_size(pci_dev); - if (limit <= addr) { - /* conventional pci device can be behind pcie-to-pci bridge. - 256 <= addr < 4K has no effects. */ - return; - } - pci_host_config_write_common(pci_dev, addr, limit, val, len); + pci_host_config_write_common(pci_dev, addr, val, len); } static uint64_t pcie_mmcfg_data_read(void *opaque, diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7f38117..f306d42 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -171,8 +171,7 @@ static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, return; } - pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), - val, size); + pci_host_config_write_common(pci_dev, addr, val, size); rtas_st(rets, 0, RTAS_OUT_SUCCESS); } diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index 72a1b8b..67e007f 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -63,7 +63,7 @@ typedef struct PCIHostBridgeClass { /* common internal helpers for PCI/PCIe hosts, cut off overflows */ void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, - uint32_t limit, uint32_t val, uint32_t len); + uint32_t val, uint32_t len); uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, uint32_t len);