From patchwork Mon Apr 25 01:23:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?7Jik7Jyg7Jew?= X-Patchwork-Id: 92689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4966DB6F17 for ; Mon, 25 Apr 2011 11:24:16 +1000 (EST) Received: from localhost ([::1]:53011 helo=lists2.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QEAX7-00021o-JZ for incoming@patchwork.ozlabs.org; Sun, 24 Apr 2011 21:24:13 -0400 Received: from eggs.gnu.org ([140.186.70.92]:57427) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QEAWy-00021W-V3 for qemu-devel@nongnu.org; Sun, 24 Apr 2011 21:24:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QEAWx-0001YM-Tk for qemu-devel@nongnu.org; Sun, 24 Apr 2011 21:24:04 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:13839) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QEAWx-0001Y0-Ii for qemu-devel@nongnu.org; Sun, 24 Apr 2011 21:24:03 -0400 Received: from epcpsbge3.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTP id <0LK6001TIP5EG680@mailout4.samsung.com> for qemu-devel@nongnu.org; Mon, 25 Apr 2011 10:23:58 +0900 (KST) X-AuditID: cbfee60d-b7c9dae000006c6e-fc-4db4cd2e14c7 Received: from epv6spt1 ( [203.254.225.135]) by epcpsbge3.samsung.com (EPCPMTA) with SMTP id 2B.80.27758.E2DC4BD4; Mon, 25 Apr 2011 10:23:58 +0900 (KST) Date: Mon, 25 Apr 2011 01:23:58 +0000 (GMT) From: YuYeon Oh To: "qemu-devel@nongnu.org" MIME-version: 1.0 X-MTR: 20110425012026401@yuyeon.oh Msgkey: 20110425012026401@yuyeon.oh X-EPLocale: ko_KR.utf-8 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-EPTrCode: X-EPTrName: X-MLAttribute: X-RootMTR: 20110425012026401@yuyeon.oh X-ParentMTR: Content-transfer-encoding: base64 Content-type: text/plain; charset=utf-8 MIME-version: 1.0 Message-id: <18082259.13471303694638277.JavaMail.weblogic@epv6ml05> X-Brightmail-Tracker: AAAAAA== X-detected-operating-system: by eggs.gnu.org: Solaris 10 (1203?) X-Received-From: 203.254.224.34 Subject: [Qemu-devel] [PATCH] target-arm: fix LDMIA bug on page boundary X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list Reply-To: yuyeon.oh@samsung.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org target-arm: fix LDMIA bug on page boundary When consecutive memory locations are on page boundary, a base register may be loaded before page fault occurs. After page fault handling, it losts the memory location information. To solve this problem, loading a base register has to put back. Signed-off-by: Yuyeon Oh Reviewed-by: Peter Maydell --- target-arm/translate.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index e1bda57..410e7c4 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7967,7 +7967,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) } } } else { - int i; + int i, loaded_base = 0; + TCGv loaded_var; /* Load/store multiple. */ addr = load_reg(s, rn); offset = 0; @@ -7979,6 +7980,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) tcg_gen_addi_i32(addr, addr, -offset); } + TCGV_UNUSED(loaded_var); for (i = 0; i < 16; i++) { if ((insn & (1 << i)) == 0) continue; @@ -7987,6 +7989,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) tmp = gen_ld32(addr, IS_USER(s)); if (i == 15) { gen_bx(s, tmp); + } else if (i == rn) { + loaded_var = tmp; + loaded_base = 1; } else { store_reg(s, i, tmp); } @@ -7997,6 +8002,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) } tcg_gen_addi_i32(addr, addr, 4); } + if (loaded_base) { + store_reg(s, rn, loaded_var); + } if (insn & (1 << 21)) { /* Base register writeback. */ if (insn & (1 << 24)) {