diff mbox series

[3/3] target/mips: implement Octeon-specific arithmetic instructions

Message ID 165459237035.143371.5795143736970750111.stgit@pasha-ThinkPad-X280
State New
Headers show
Series Cavium Octeon MIPS extensions | expand

Commit Message

Pavel Dovgalyuk June 7, 2022, 8:59 a.m. UTC 
This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
---
 target/mips/helper.h                |    1 
 target/mips/tcg/meson.build         |    1 
 target/mips/tcg/octeon.decode       |   25 +++++
 target/mips/tcg/octeon_helper.c     |   22 ++++
 target/mips/tcg/octeon_helper.h.inc |   10 ++
 target/mips/tcg/octeon_translate.c  |  182 +++++++++++++++++++++++++++++++++++
 6 files changed, 241 insertions(+)
 create mode 100644 target/mips/tcg/octeon_helper.c
 create mode 100644 target/mips/tcg/octeon_helper.h.inc

Comments

Richard Henderson June 7, 2022, 5:16 p.m. UTC | #1 
On 6/7/22 01:59, Pavel Dovgalyuk wrote:
> +static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
> +{
> +    TCGv t0, t1;
> +    int p;
> +    TCGLabel *l1;
> +
> +    if (a->rt == 0) {
> +        /* nop */
> +        return true;
> +    }
> +
> +    p = a->p;
> +    if (a->shift) {
> +        p += 32;
> +    }
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +    gen_load_gpr(t1, a->rs);
> +
> +    tcg_gen_movi_tl(t0, ((1ULL << (a->lenm1 + 1)) - 1) << p);
> +    tcg_gen_and_tl(t1, t1, t0);
> +    tcg_gen_movi_tl(t0, p);
> +    tcg_gen_shr_tl(cpu_gpr[a->rt], t1, t0);
> +
> +    l1 = gen_new_label();
> +    tcg_gen_movi_tl(t0, 1ULL << a->lenm1);
> +    tcg_gen_and_tl(t0, cpu_gpr[a->rt], t0);
> +    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
> +    tcg_gen_movi_tl(t0, ~((1ULL << (a->lenm1 + 1)) - 1));
> +    tcg_gen_or_tl(cpu_gpr[a->rt], cpu_gpr[a->rt], t0);
> +    gen_set_label(l1);

This is tcg_gen_sextract_tl.

> +static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
> +{
> +    TCGv t0, t1;
> +
> +    if (a->rt == 0) {
> +        /* nop */
> +        return true;
> +    }
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +    gen_load_gpr(t1, a->rs);
> +
> +    tcg_gen_movi_tl(t0, (1ULL << (a->lenm1 + 1)) - 1);
> +    tcg_gen_and_tl(t1, t1, t0);
> +    tcg_gen_movi_tl(t0, a->p + a->shift ? 32 : 0);
> +    tcg_gen_shl_tl(cpu_gpr[a->rt], t1, t0);

This is tcg_gen_deposit_z_tl.

> +static bool trans_POP(DisasContext *ctx, arg_POP *a)
> +{
> +    TCGv t0;
> +
> +    if (a->rd == 0) {
> +        /* nop */
> +        return true;
> +    }
> +
> +    t0 = tcg_temp_new();
> +    gen_load_gpr(t0, a->rs);
> +    if (!a->dw) {
> +        tcg_gen_andi_i64(t0, t0, 0xffffffff);
> +    }
> +    gen_helper_pop(cpu_gpr[a->rd], t0);

This is tcg_gen_ctpop_tl.


r~
diff mbox series

Patch

diff --git a/target/mips/helper.h b/target/mips/helper.h
index de32d82e98..d68abdeac1 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -597,3 +597,4 @@  DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
 
 /* Vendor extensions */
 #include "tcg/vr54xx_helper.h.inc"
+#include "tcg/octeon_helper.h.inc"
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index 7ee969ec8f..1852366846 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -26,6 +26,7 @@  mips_ss.add(files(
 mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
   'tx79_translate.c',
   'octeon_translate.c',
+  'octeon_helper.c',
 ), if_false: files(
   'mxu_translate.c',
 ))
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index c06d576292..ababf59e42 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -12,3 +12,28 @@ 
 # BBIT132    111110 ..... ..... ................
 
 BBIT         11 set:1 shift:1 10 rs:5 p:5 offset:16
+
+# Arithmetic
+# BADDU rd, rs, rt
+# DMUL rd, rs, rt
+# EXTS rt, rs, p, lenm1
+# EXTS32 rt, rs, p, lenm1
+# CINS rt, rs, p, lenm1
+# CINS32 rt, rs, p, lenm1
+# DPOP rd, rs
+# POP rd, rs
+# SEQ rd, rs, rt
+# SEQI rt, rs, immediate
+# SNE rd, rs, rt
+# SNEI rt, rs, immediate
+
+@r3          ...... rs:5 rt:5 rd:5 ..... ......
+@bitfield    ...... rs:5 rt:5 lenm1:5 p:5 ..... shift:1
+
+BADDU        011100 ..... ..... ..... 00000 101000 @r3
+DMUL         011100 ..... ..... ..... 00000 000011 @r3
+EXTS         011100 ..... ..... ..... ..... 11101 . @bitfield
+CINS         011100 ..... ..... ..... ..... 11001 . @bitfield
+POP          011100 rs:5 00000 rd:5 00000 10110 dw:1
+SEQNE        011100 rs:5 rt:5 rd:5 00000 10101 ne:1
+SEQNEI       011100 rs:5 rt:5 imm:s10 10111 ne:1
diff --git a/target/mips/tcg/octeon_helper.c b/target/mips/tcg/octeon_helper.c
new file mode 100644
index 0000000000..e9650c58bd
--- /dev/null
+++ b/target/mips/tcg/octeon_helper.c
@@ -0,0 +1,22 @@ 
+/*
+ *  MIPS Octeon emulation helpers
+ *
+ *  Copyright (c) 2022 Pavel Dovgalyuk
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+
+target_ulong helper_pop(target_ulong arg)
+{
+    int i;
+    int res = 0;
+    for (i = 0 ; i < 64 ; ++i) {
+        res += arg & 1;
+        arg >>= 1;
+    }
+
+    return res;
+}
diff --git a/target/mips/tcg/octeon_helper.h.inc b/target/mips/tcg/octeon_helper.h.inc
new file mode 100644
index 0000000000..cfc051ef47
--- /dev/null
+++ b/target/mips/tcg/octeon_helper.h.inc
@@ -0,0 +1,10 @@ 
+/*
+ *  MIPS Octeon emulation helpers
+ *
+ *  Copyright (c) 2022 Pavel Dovgalyuk
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#if defined(TARGET_MIPS64)
+DEF_HELPER_1(pop, tl, tl)
+#endif
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index bd87066b01..c4ef3e5bcb 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -51,3 +51,185 @@  static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
     tcg_temp_free(t0);
     return true;
 }
+
+static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
+{
+    TCGv t0, t1;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    gen_load_gpr(t1, a->rt);
+
+    tcg_gen_add_tl(t0, t0, t1);
+    tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
+{
+    TCGv t0, t1;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    gen_load_gpr(t1, a->rt);
+
+    tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
+{
+    TCGv t0, t1;
+    int p;
+    TCGLabel *l1;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    p = a->p;
+    if (a->shift) {
+        p += 32;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+    gen_load_gpr(t1, a->rs);
+
+    tcg_gen_movi_tl(t0, ((1ULL << (a->lenm1 + 1)) - 1) << p);
+    tcg_gen_and_tl(t1, t1, t0);
+    tcg_gen_movi_tl(t0, p);
+    tcg_gen_shr_tl(cpu_gpr[a->rt], t1, t0);
+
+    l1 = gen_new_label();
+    tcg_gen_movi_tl(t0, 1ULL << a->lenm1);
+    tcg_gen_and_tl(t0, cpu_gpr[a->rt], t0);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
+    tcg_gen_movi_tl(t0, ~((1ULL << (a->lenm1 + 1)) - 1));
+    tcg_gen_or_tl(cpu_gpr[a->rt], cpu_gpr[a->rt], t0);
+    gen_set_label(l1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
+{
+    TCGv t0, t1;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+    gen_load_gpr(t1, a->rs);
+
+    tcg_gen_movi_tl(t0, (1ULL << (a->lenm1 + 1)) - 1);
+    tcg_gen_and_tl(t1, t1, t0);
+    tcg_gen_movi_tl(t0, a->p + a->shift ? 32 : 0);
+    tcg_gen_shl_tl(cpu_gpr[a->rt], t1, t0);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_POP(DisasContext *ctx, arg_POP *a)
+{
+    TCGv t0;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    if (!a->dw) {
+        tcg_gen_andi_i64(t0, t0, 0xffffffff);
+    }
+    gen_helper_pop(cpu_gpr[a->rd], t0);
+
+    tcg_temp_free(t0);
+
+    return true;
+}
+
+static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
+{
+    TCGv t0, t1;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+
+    gen_load_gpr(t0, a->rs);
+    gen_load_gpr(t1, a->rt);
+
+    if (a->ne) {
+        tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);
+    } else {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
+    }
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
+{
+    TCGv t0;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+
+    gen_load_gpr(t0, a->rs);
+
+    /* Sign-extend to 64 bit value */
+    target_ulong imm = a->imm;
+    if (a->ne) {
+        tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
+    } else {
+        tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
+    }
+
+    tcg_temp_free(t0);
+
+    return true;
+}