diff mbox series

[v8,28/29] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts

Message ID 1635760311-20015-29-git-send-email-gaosong@loongson.cn
State New
Headers show
Series Add LoongArch linux-user emulation support | expand

Commit Message

Song Gao Nov. 1, 2021, 9:51 a.m. UTC
Base-on: <20210925173032.2434906-30-git@xen0n.name>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 accel/tcg/user-exec.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 61 insertions(+), 3 deletions(-)

Comments

WANG Xuerui Nov. 1, 2021, 10:45 a.m. UTC | #1
Hi,

On 2021/11/1 17:51, Song Gao wrote:
> Base-on: <20210925173032.2434906-30-git@xen0n.name>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> ---
>  accel/tcg/user-exec.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 61 insertions(+), 3 deletions(-)

While I can see this patch and the next one are clearly from me, my
author info is lost as I didn't spot any "From:" line in the mail body?
Also I don't remember seeing "Base-on" tags in QEMU either.

I think you're meaning to include the "Based-on" tags in your cover
letter instead?
Song Gao Nov. 1, 2021, 11:21 a.m. UTC | #2
Hi Xuerui,

On 2021/11/1 下午6:45, WANG Xuerui wrote:
> While I can see this patch and the next one are clearly from me, my
> author info is lost as I didn't spot any "From:" line in the mail body?
> Also I don't remember seeing "Base-on" tags in QEMU either.

Sorry,  I refer to the commit 35f171a2eb25fcdf1b719c58a61a7da15b4fe078

It seems that the reference is wrong.  I 'll correct it.

> I think you're meaning to include the "Based-on" tags in your cover
> letter instead?

I should take this way,  Sorry Again,
WANG Xuerui Nov. 2, 2021, 3:18 a.m. UTC | #3
Hi,

On 2021/11/1 19:21, gaosong wrote:
> Hi Xuerui,
>
> On 2021/11/1 下午6:45, WANG Xuerui wrote:
>> While I can see this patch and the next one are clearly from me, my
>> author info is lost as I didn't spot any "From:" line in the mail body?
>> Also I don't remember seeing "Base-on" tags in QEMU either.
>
> Sorry,  I refer to the commit 35f171a2eb25fcdf1b719c58a61a7da15b4fe078
>
> It seems that the reference is wrong.  I 'll correct it.
My patch series haven't gone into upstream yet, so I'm pretty sure this
commit hash would change in the final merged version. I think basing
your whole series on top of mine should be okay; mine has been
completely reviewed and IIUC only waiting for a test-purpose Docker
builder image before it can be merged, so the code should be fairly
stable and friendly for rebases.
>
>> I think you're meaning to include the "Based-on" tags in your cover
>> letter instead?
>
> I should take this way,  Sorry Again,
>
Never mind; you could of course use more caution when it comes to Git
operations later.
diff mbox series

Patch

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 7604b0a..ec887c4 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -811,10 +811,68 @@  int cpu_signal_handler(int host_signum, void *pinfo,
     siginfo_t *info = pinfo;
     ucontext_t *uc = puc;
     greg_t pc = uc->uc_mcontext.__pc;
-    int is_write;
+    uint32_t insn = *(uint32_t *)pc;
+    int is_write = 0;
+
+    /* Detect store by reading the instruction at the program counter. */
+    switch ((insn >> 26) & 0b111111) {
+    case 0b001000: /* {ll,sc}.[wd] */
+        switch ((insn >> 24) & 0b11) {
+        case 0b01: /* sc.w */
+        case 0b11: /* sc.d */
+            is_write = 1;
+            break;
+        }
+        break;
+    case 0b001001: /* {ld,st}ox4.[wd] ({ld,st}ptr.[wd]) */
+        switch ((insn >> 24) & 0b11) {
+        case 0b01: /* stox4.w (stptr.w) */
+        case 0b11: /* stox4.d (stptr.d) */
+            is_write = 1;
+            break;
+        }
+        break;
+    case 0b001010: /* {ld,st}.* family */
+        switch ((insn >> 22) & 0b1111) {
+        case 0b0100: /* st.b */
+        case 0b0101: /* st.h */
+        case 0b0110: /* st.w */
+        case 0b0111: /* st.d */
+        case 0b1101: /* fst.s */
+        case 0b1111: /* fst.d */
+            is_write = 1;
+            break;
+        }
+        break;
+    case 0b001110: /* indexed, atomic, bounds-checking memory operations */
+        uint32_t sel = (insn >> 15) & 0b11111111111;
+
+        switch (sel) {
+        case 0b00000100000: /* stx.b */
+        case 0b00000101000: /* stx.h */
+        case 0b00000110000: /* stx.w */
+        case 0b00000111000: /* stx.d */
+        case 0b00001110000: /* fstx.s */
+        case 0b00001111000: /* fstx.d */
+        case 0b00011101100: /* fstgt.s */
+        case 0b00011101101: /* fstgt.d */
+        case 0b00011101110: /* fstle.s */
+        case 0b00011101111: /* fstle.d */
+        case 0b00011111000: /* stgt.b */
+        case 0b00011111001: /* stgt.h */
+        case 0b00011111010: /* stgt.w */
+        case 0b00011111011: /* stgt.d */
+        case 0b00011111100: /* stle.b */
+        case 0b00011111101: /* stle.h */
+        case 0b00011111110: /* stle.w */
+        case 0b00011111111: /* stle.d */
+        case 0b00011000000 ... 0b00011100011: /* am* insns */
+            is_write = 1;
+            break;
+        }
+        break;
+    }
 
-    /* XXX: compute is_write */
-    is_write = 0;
     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }