Message ID | 1606709124-80741-2-git-send-email-bmeng.cn@gmail.com |
---|---|
State | Superseded |
Headers | show |
Series | [1/2] hw/ssi: imx_spi: Use a macro for number of chip selects supported | expand |
On Sun, Nov 29, 2020 at 8:05 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Xuzhou Cheng <xuzhou.cheng@windriver.com> > > When a write to ECSPI_CONREG register to disable the SPI controller, > imx_spi_reset() is called to reset the controller, during which CS > lines should have been disabled, otherwise the state machine of any > devices (e.g.: SPI flashes) connected to the SPI master is stuck to > its last state and responds incorrectly to any follow-up commands. > > Fixes c906a3a01582: ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> > Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > hw/ssi/imx_spi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index e605049..85c172e 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -231,6 +231,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > static void imx_spi_reset(DeviceState *dev) > { > IMXSPIState *s = IMX_SPI(dev); > + int i; > > DPRINTF("\n"); > > @@ -243,6 +244,10 @@ static void imx_spi_reset(DeviceState *dev) > > imx_spi_update_irq(s); > > + for (i = 0; i < ECSPI_NUM_CS; i++) { > + qemu_set_irq(s->cs_lines[i], 1); > + } > + > s->burst_length = 0; > } > > -- > 2.7.4 > >
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049..85c172e 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -231,6 +231,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + int i; DPRINTF("\n"); @@ -243,6 +244,10 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_update_irq(s); + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length = 0; }