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[V16,2/6] target/mips: Add unaligned access support for MIPS64R6 and Loongson-3

Message ID 1604053541-27822-3-git-send-email-chenhc@lemote.com
State New
Headers show
Series mips: Add Loongson-3 machine support | expand

Commit Message

Huacai Chen Oct. 30, 2020, 10:25 a.m. UTC
MIPSR6 (not only MIPS32R6) processors support unaligned access in
hardware, so set MO_UNALN in their default_tcg_memop_mask. Btw, new
Loongson-3 (such as Loongson-3A4000) also support unaligned access,
since both old and new Loongson-3 use the same binaries, we can simply
set MO_UNALN for all Loongson-3 processors.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 target/mips/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Philippe Mathieu-Daudé Nov. 3, 2020, 12:47 p.m. UTC | #1
On 10/30/20 11:25 AM, Huacai Chen wrote:
> MIPSR6 (not only MIPS32R6) processors support unaligned access in
> hardware, so set MO_UNALN in their default_tcg_memop_mask. Btw, new
> Loongson-3 (such as Loongson-3A4000) also support unaligned access,
> since both old and new Loongson-3 use the same binaries, we can simply
> set MO_UNALN for all Loongson-3 processors.
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
>  target/mips/translate.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index f449758..470f59c 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -31442,8 +31442,8 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>  #else
>          ctx->mem_idx = hflags_mmu_index(ctx->hflags);
>  #endif
> -    ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
> -                                  MO_UNALN : MO_ALIGN;
> +    ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 |
> +                                  INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
>  
>      LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
>                ctx->hflags);
> 

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

And queued to mips-next.
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Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index f449758..470f59c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31442,8 +31442,8 @@  static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #else
         ctx->mem_idx = hflags_mmu_index(ctx->hflags);
 #endif
-    ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
-                                  MO_UNALN : MO_ALIGN;
+    ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 |
+                                  INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
 
     LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
               ctx->hflags);