From patchwork Thu Oct 29 23:58:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 1390503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcdkim header.b=WS+FH5Nc; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CMjGg2lGvz9sSG for ; Fri, 30 Oct 2020 11:04:27 +1100 (AEDT) Received: from localhost ([::1]:43150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kYHu5-00055F-6g for incoming@patchwork.ozlabs.org; Thu, 29 Oct 2020 20:04:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kYHp1-0008TC-Sj for qemu-devel@nongnu.org; Thu, 29 Oct 2020 19:59:11 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:45885) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kYHoz-0004LV-EK for qemu-devel@nongnu.org; Thu, 29 Oct 2020 19:59:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604015949; x=1635551949; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3oQkrRpo7U0k1j06uRl+Ko8wJbT7hHLbi+yTj6D9sHY=; b=WS+FH5NcR5aa/F+cFIIEmS49uodBiY5cMqq6BQi1gRNhbJWHSqh8Sd8E qXLp56A+KP3BEAxOxzYRm2YemY6XwTNNg+dC8WXIuGLOwLNda2UVCz7UV aQlXhBp3Os6zoNPeeFoRkEPgc/VBlAEeteHsuLEB7rFG4nQ8KJu+yR1IW 8=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 29 Oct 2020 16:59:01 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 29 Oct 2020 16:58:59 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id EA0AC40D0; Thu, 29 Oct 2020 18:58:52 -0500 (CDT) From: Taylor Simpson To: tsimpson@quicinc.com Subject: [RFC PATCH v5 06/33] Hexagon (target/hexagon) register names Date: Thu, 29 Oct 2020 18:58:23 -0500 Message-Id: <1604015931-23005-7-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> References: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:All patches CC here" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/hex_regs.h | 83 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 target/hexagon/hex_regs.h diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h new file mode 100644 index 0000000..3b4249a --- /dev/null +++ b/target/hexagon/hex_regs.h @@ -0,0 +1,83 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_REGS_H +#define HEXAGON_REGS_H + +enum { + HEX_REG_R00 = 0, + HEX_REG_R01 = 1, + HEX_REG_R02 = 2, + HEX_REG_R03 = 3, + HEX_REG_R04 = 4, + HEX_REG_R05 = 5, + HEX_REG_R06 = 6, + HEX_REG_R07 = 7, + HEX_REG_R08 = 8, + HEX_REG_R09 = 9, + HEX_REG_R10 = 10, + HEX_REG_R11 = 11, + HEX_REG_R12 = 12, + HEX_REG_R13 = 13, + HEX_REG_R14 = 14, + HEX_REG_R15 = 15, + HEX_REG_R16 = 16, + HEX_REG_R17 = 17, + HEX_REG_R18 = 18, + HEX_REG_R19 = 19, + HEX_REG_R20 = 20, + HEX_REG_R21 = 21, + HEX_REG_R22 = 22, + HEX_REG_R23 = 23, + HEX_REG_R24 = 24, + HEX_REG_R25 = 25, + HEX_REG_R26 = 26, + HEX_REG_R27 = 27, + HEX_REG_R28 = 28, + HEX_REG_R29 = 29, + HEX_REG_SP = 29, + HEX_REG_FP = 30, + HEX_REG_R30 = 30, + HEX_REG_LR = 31, + HEX_REG_R31 = 31, + HEX_REG_SA0 = 32, + HEX_REG_LC0 = 33, + HEX_REG_SA1 = 34, + HEX_REG_LC1 = 35, + HEX_REG_P3_0 = 36, + HEX_REG_M0 = 38, + HEX_REG_M1 = 39, + HEX_REG_USR = 40, + HEX_REG_PC = 41, + HEX_REG_UGP = 42, + HEX_REG_GP = 43, + HEX_REG_CS0 = 44, + HEX_REG_CS1 = 45, + HEX_REG_UPCYCLELO = 46, + HEX_REG_UPCYCLEHI = 47, + HEX_REG_FRAMELIMIT = 48, + HEX_REG_FRAMEKEY = 49, + HEX_REG_PKTCNTLO = 50, + HEX_REG_PKTCNTHI = 51, + /* Use reserved control registers for qemu execution counts */ + HEX_REG_QEMU_PKT_CNT = 52, + HEX_REG_QEMU_INSN_CNT = 53, + HEX_REG_UTIMERLO = 62, + HEX_REG_UTIMERHI = 63, +}; + +#endif