From patchwork Mon Sep 28 12:36:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 1372636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcdkim header.b=Qh7KBTXE; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C0NJp3mFfz9s1t for ; Mon, 28 Sep 2020 23:14:18 +1000 (AEST) Received: from localhost ([::1]:59322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kMsyu-0000QU-ER for incoming@patchwork.ozlabs.org; Mon, 28 Sep 2020 09:14:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kMsPZ-0004lN-V2 for qemu-devel@nongnu.org; Mon, 28 Sep 2020 08:37:47 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:46899) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kMsPJ-0005eW-6j for qemu-devel@nongnu.org; Mon, 28 Sep 2020 08:37:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1601296649; x=1632832649; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZiEqm7QDBf6sEbIo+0hvD6v0gWUWriKMCx7asZbqFt8=; b=Qh7KBTXEwGz5KpHfkCOLIMbQkCjiTGo8G3dtb088frjVSDyuknMwxoh5 qgWYZQPwDSfdy9A65jKgh70lm1IpTbtNrRlnKQKuefXPFQoYVWeI+COFq pjhu0CHbgItBKXudu7kj5YMGe6qCDpHUWlPbtUKrM5MnG0rK51sIMl8by 4=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 28 Sep 2020 05:36:55 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 28 Sep 2020 05:36:55 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 7697DCE1; Mon, 28 Sep 2020 07:36:55 -0500 (CDT) From: Taylor Simpson To: tsimpson@quicinc.com Subject: [RFC PATCH v4 29/29] Hexagon build infrastructure Date: Mon, 28 Sep 2020 07:36:48 -0500 Message-Id: <1601296608-29390-30-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601296608-29390-1-git-send-email-tsimpson@quicinc.com> References: <1601296608-29390-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/28 08:36:52 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.199, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , "open list:All patches CC here" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add file to default-configs Change configure Add hexagon to meson.build Add hexagon to target/meson.build Add target/hexagon/meson.build Change scripts/qemu-binfmt-conf.sh We can build a hexagon-linux-user target and run programs on the Hexagon scalar core. With hexagon-linux-clang installed, "make check-tcg" will pass. Signed-off-by: Taylor Simpson --- configure | 6 ++ default-configs/hexagon-linux-user.mak | 1 + meson.build | 1 + scripts/qemu-binfmt-conf.sh | 6 +- target/hexagon/meson.build | 178 +++++++++++++++++++++++++++++++++ target/meson.build | 1 + 6 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 default-configs/hexagon-linux-user.mak create mode 100644 target/hexagon/meson.build diff --git a/configure b/configure index e8e8e98..e57eb1b 100755 --- a/configure +++ b/configure @@ -7727,6 +7727,12 @@ case "$target_name" in bflt="yes" mttcg="yes" ;; + hexagon) + TARGET_BASE_ARCH=hexagon + TARGET_ABI_DIR=hexagon + mttcg=yes + target_compiler=$cross_cc_hexagon + ;; *) error_exit "Unsupported target CPU" ;; diff --git a/default-configs/hexagon-linux-user.mak b/default-configs/hexagon-linux-user.mak new file mode 100644 index 0000000..ad55af0 --- /dev/null +++ b/default-configs/hexagon-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for hexagon-linux-user diff --git a/meson.build b/meson.build index f4d1ab1..f401838 100644 --- a/meson.build +++ b/meson.build @@ -485,6 +485,7 @@ disassemblers = { 'arm' : ['CONFIG_ARM_DIS'], 'avr' : ['CONFIG_AVR_DIS'], 'cris' : ['CONFIG_CRIS_DIS'], + 'hexagon' : ['CONFIG_HEXAGON_DIS'], 'hppa' : ['CONFIG_HPPA_DIS'], 'i386' : ['CONFIG_I386_DIS'], 'x86_64' : ['CONFIG_I386_DIS'], diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 9f1580a..7b5d54b 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -4,7 +4,7 @@ qemu_target_list="i386 i486 alpha arm armeb sparc sparc32plus sparc64 \ ppc ppc64 ppc64le m68k mips mipsel mipsn32 mipsn32el mips64 mips64el \ sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \ -microblaze microblazeel or1k x86_64" +microblaze microblazeel or1k x86_64 hexagon" i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00' i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' @@ -136,6 +136,10 @@ or1k_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\ or1k_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff' or1k_family=or1k +hexagon_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xa4\x00' +hexagon_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' +hexagon_family=hexagon + qemu_get_family() { cpu=${HOST_ARCH:-$(uname -m)} case "$cpu" in diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build new file mode 100644 index 0000000..8ff5cf6 --- /dev/null +++ b/target/hexagon/meson.build @@ -0,0 +1,178 @@ +## +## Copyright(c) 2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +hexagon_ss = ss.source_set() + +prog_python = import('python').find_installation('python3') + +hex_common_py = 'hex_common.py' +attribs_def_h = meson.current_source_dir() / 'attribs_def.h' +gen_tcg_h = meson.current_source_dir() / 'gen_tcg.h' + +# +# Step 1 +# We use a C program to create semantics_generated.pyinc +# +gen_semantics = executable('gen_semantics', 'gen_semantics.c') + +semantics = custom_target( + 'semantics_generated.pyinc', + output: 'semantics_generated.pyinc', + input: gen_semantics, + command: ['@INPUT@', '@OUTPUT@'], +) +hexagon_ss.add(semantics) + +# +# Step 2 +# We use Python scripts to generate the following files +# shortcode_generated.h +# helper_protos_generated.h +# tcg_funcs_generated.h +# tcg_func_table_generated.h +# helper_funcs_generated.h +# printinsn_generated.h +# op_regs_generated.h +# op_attribs_generated.h +# opcodes_def_generated.h +# +shortcode_h = custom_target( + 'shortcode_generated.h', + output: 'shortcode_generated.h', + input: 'gen_shortcode.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, '@OUTPUT@'], +) +hexagon_ss.add(shortcode_h) + +helper_protos_h = custom_target( + 'helper_protos_generated.h', + output: 'helper_protos_generated.h', + input: 'gen_helper_protos.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, gen_tcg_h, '@OUTPUT@'], +) +hexagon_ss.add(helper_protos_h) + +tcg_funcs_h = custom_target( + 'tcg_funcs_generated.h', + output: 'tcg_funcs_generated.h', + input: 'gen_tcg_funcs.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, gen_tcg_h, '@OUTPUT@'], +) +hexagon_ss.add(tcg_funcs_h) + +tcg_func_table_h = custom_target( + 'tcg_func_table_generated.h', + output: 'tcg_func_table_generated.h', + input: 'gen_tcg_func_table.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, '@OUTPUT@'], +) +hexagon_ss.add(tcg_func_table_h) + +helper_funcs_h = custom_target( + 'helper_funcs_generated.h', + output: 'helper_funcs_generated.h', + input: 'gen_helper_funcs.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, gen_tcg_h, '@OUTPUT@'], +) +hexagon_ss.add(helper_funcs_h) + +printinsn_h = custom_target( + 'printinsn_generated.h', + output: 'printinsn_generated.h', + input: 'gen_printinsn.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, '@OUTPUT@'], +) +hexagon_ss.add(printinsn_h) + +op_regs_h = custom_target( + 'op_regs_generated.h', + output: 'op_regs_generated.h', + input: 'gen_op_regs.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, '@OUTPUT@'], +) +hexagon_ss.add(op_regs_h) + +op_attribs_h = custom_target( + 'op_attribs_generated.h', + output: 'op_attribs_generated.h', + input: 'gen_op_attribs.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, '@OUTPUT@'], +) +hexagon_ss.add(op_attribs_h) + +opcodes_def_h = custom_target( + 'opcodes_def_generated.h', + output: 'opcodes_def_generated.h', + input: 'gen_opcodes_def.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics, attribs_def_h, '@OUTPUT@'], +) +hexagon_ss.add(opcodes_def_h) + +# +# Step 3 +# We use a C program to create iset.py which is imported into dectree.py +# to create the decode tree +# +gen_dectree_import = executable('gen_dectree_import', 'gen_dectree_import.c', opcodes_def_h, op_regs_h) + +iset_py = custom_target( + 'iset.py', + output: 'iset.py', + input: gen_dectree_import, + command: ['@INPUT@', '@OUTPUT@'], +) +hexagon_ss.add(iset_py) + +# +# Step 4 +# We use the dectree.py script to generate the decode tree header file +# +dectree_h = custom_target( + 'dectree_generated.h', + output: 'dectree_generated.h', + input: 'dectree.py', + depends: [iset_py], + command: ['PYTHONPATH=' + meson.current_build_dir(), '@INPUT@', '@OUTPUT@'], +) +hexagon_ss.add(dectree_h) + +hexagon_ss.add(files( + 'cpu.c', + 'translate.c', + 'op_helper.c', + 'gdbstub.c', + 'genptr.c', + 'reg_fields.c', + 'decode.c', + 'iclass.c', + 'opcodes.c', + 'printinsn.c', + 'arch.c', + 'fma_emu.c', + 'conv_emu.c', +)) + +target_arch += {'hexagon': hexagon_ss} diff --git a/target/meson.build b/target/meson.build index 9f0ae93..c35c1e9 100644 --- a/target/meson.build +++ b/target/meson.build @@ -2,6 +2,7 @@ subdir('alpha') subdir('arm') subdir('avr') subdir('cris') +subdir('hexagon') subdir('hppa') subdir('i386') subdir('lm32')